139faeba7SSowjanya Komatineni# SPDX-License-Identifier: GPL-2.0 239faeba7SSowjanya Komatineni%YAML 1.2 339faeba7SSowjanya Komatineni--- 439faeba7SSowjanya Komatineni$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 539faeba7SSowjanya Komatineni$schema: http://devicetree.org/meta-schemas/core.yaml# 639faeba7SSowjanya Komatineni 739faeba7SSowjanya Komatinenititle: Tegra Power Management Controller (PMC) 839faeba7SSowjanya Komatineni 939faeba7SSowjanya Komatinenimaintainers: 1039faeba7SSowjanya Komatineni - Thierry Reding <thierry.reding@gmail.com> 1139faeba7SSowjanya Komatineni - Jonathan Hunter <jonathanh@nvidia.com> 1239faeba7SSowjanya Komatineni 1339faeba7SSowjanya Komatineniproperties: 1439faeba7SSowjanya Komatineni compatible: 1539faeba7SSowjanya Komatineni enum: 1639faeba7SSowjanya Komatineni - nvidia,tegra20-pmc 1739faeba7SSowjanya Komatineni - nvidia,tegra20-pmc 1839faeba7SSowjanya Komatineni - nvidia,tegra30-pmc 1939faeba7SSowjanya Komatineni - nvidia,tegra114-pmc 2039faeba7SSowjanya Komatineni - nvidia,tegra124-pmc 2139faeba7SSowjanya Komatineni - nvidia,tegra210-pmc 2239faeba7SSowjanya Komatineni 2339faeba7SSowjanya Komatineni reg: 2439faeba7SSowjanya Komatineni maxItems: 1 2539faeba7SSowjanya Komatineni description: 2639faeba7SSowjanya Komatineni Offset and length of the register set for the device. 2739faeba7SSowjanya Komatineni 2839faeba7SSowjanya Komatineni clock-names: 2939faeba7SSowjanya Komatineni items: 3039faeba7SSowjanya Komatineni - const: pclk 3139faeba7SSowjanya Komatineni - const: clk32k_in 3239faeba7SSowjanya Komatineni description: 3339faeba7SSowjanya Komatineni Must includes entries pclk and clk32k_in. 3439faeba7SSowjanya Komatineni pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 3539faeba7SSowjanya Komatineni input to Tegra. 3639faeba7SSowjanya Komatineni 3739faeba7SSowjanya Komatineni clocks: 3839faeba7SSowjanya Komatineni maxItems: 2 3939faeba7SSowjanya Komatineni description: 4039faeba7SSowjanya Komatineni Must contain an entry for each entry in clock-names. 4139faeba7SSowjanya Komatineni See ../clocks/clocks-bindings.txt for details. 4239faeba7SSowjanya Komatineni 43f85fa319SSowjanya Komatineni '#clock-cells': 44f85fa319SSowjanya Komatineni const: 1 45f85fa319SSowjanya Komatineni description: 46f85fa319SSowjanya Komatineni Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 47cd88f167SSowjanya Komatineni PMC also has blink control which allows 32Khz clock output to 48cd88f167SSowjanya Komatineni Tegra blink pad. 49f85fa319SSowjanya Komatineni Consumer of PMC clock should specify the desired clock by having 50f85fa319SSowjanya Komatineni the clock ID in its "clocks" phandle cell with pmc clock provider. 51f85fa319SSowjanya Komatineni See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 52f85fa319SSowjanya Komatineni clock IDs. 53f85fa319SSowjanya Komatineni 5439faeba7SSowjanya Komatineni '#interrupt-cells': 5539faeba7SSowjanya Komatineni const: 2 5639faeba7SSowjanya Komatineni description: 5739faeba7SSowjanya Komatineni Specifies number of cells needed to encode an interrupt source. 5839faeba7SSowjanya Komatineni The value must be 2. 5939faeba7SSowjanya Komatineni 6039faeba7SSowjanya Komatineni interrupt-controller: true 6139faeba7SSowjanya Komatineni 6239faeba7SSowjanya Komatineni nvidia,invert-interrupt: 6339faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 6439faeba7SSowjanya Komatineni description: Inverts the PMU interrupt signal. 6539faeba7SSowjanya Komatineni The PMU is an external Power Management Unit, whose interrupt output 6639faeba7SSowjanya Komatineni signal is fed into the PMC. This signal is optionally inverted, and 6739faeba7SSowjanya Komatineni then fed into the ARM GIC. The PMC is not involved in the detection 6839faeba7SSowjanya Komatineni or handling of this interrupt signal, merely its inversion. 6939faeba7SSowjanya Komatineni 7039faeba7SSowjanya Komatineni nvidia,core-power-req-active-high: 7139faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 7239faeba7SSowjanya Komatineni description: Core power request active-high. 7339faeba7SSowjanya Komatineni 7439faeba7SSowjanya Komatineni nvidia,sys-clock-req-active-high: 7539faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 7639faeba7SSowjanya Komatineni description: System clock request active-high. 7739faeba7SSowjanya Komatineni 7839faeba7SSowjanya Komatineni nvidia,combined-power-req: 7939faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 8039faeba7SSowjanya Komatineni description: combined power request for CPU and Core. 8139faeba7SSowjanya Komatineni 8239faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-en: 8339faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 8439faeba7SSowjanya Komatineni description: 8539faeba7SSowjanya Komatineni CPU power good signal from external PMIC to PMC is enabled. 8639faeba7SSowjanya Komatineni 8739faeba7SSowjanya Komatineni nvidia,suspend-mode: 8839faeba7SSowjanya Komatineni allOf: 8939faeba7SSowjanya Komatineni - $ref: /schemas/types.yaml#/definitions/uint32 9039faeba7SSowjanya Komatineni - enum: [0, 1, 2] 9139faeba7SSowjanya Komatineni description: 9239faeba7SSowjanya Komatineni The suspend mode that the platform should use. 9339faeba7SSowjanya Komatineni Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 9439faeba7SSowjanya Komatineni Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 9539faeba7SSowjanya Komatineni Mode 2 is for LP2, CPU voltage off 9639faeba7SSowjanya Komatineni 9739faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-time: 9839faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 9939faeba7SSowjanya Komatineni description: CPU power good time in uSec. 10039faeba7SSowjanya Komatineni 10139faeba7SSowjanya Komatineni nvidia,cpu-pwr-off-time: 10239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 10339faeba7SSowjanya Komatineni description: CPU power off time in uSec. 10439faeba7SSowjanya Komatineni 10539faeba7SSowjanya Komatineni nvidia,core-pwr-good-time: 10639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32-array 10739faeba7SSowjanya Komatineni description: 10839faeba7SSowjanya Komatineni <Oscillator-stable-time Power-stable-time> 10939faeba7SSowjanya Komatineni Core power good time in uSec. 11039faeba7SSowjanya Komatineni 11139faeba7SSowjanya Komatineni nvidia,core-pwr-off-time: 11239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 11339faeba7SSowjanya Komatineni description: Core power off time in uSec. 11439faeba7SSowjanya Komatineni 11539faeba7SSowjanya Komatineni nvidia,lp0-vec: 11639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32-array 11739faeba7SSowjanya Komatineni description: 11839faeba7SSowjanya Komatineni <start length> Starting address and length of LP0 vector. 11939faeba7SSowjanya Komatineni The LP0 vector contains the warm boot code that is executed 12039faeba7SSowjanya Komatineni by AVP when resuming from the LP0 state. 12139faeba7SSowjanya Komatineni The AVP (Audio-Video Processor) is an ARM7 processor and 12239faeba7SSowjanya Komatineni always being the first boot processor when chip is power on 12339faeba7SSowjanya Komatineni or resume from deep sleep mode. When the system is resumed 12439faeba7SSowjanya Komatineni from the deep sleep mode, the warm boot code will restore 12539faeba7SSowjanya Komatineni some PLLs, clocks and then brings up CPU0 for resuming the 12639faeba7SSowjanya Komatineni system. 12739faeba7SSowjanya Komatineni 12839faeba7SSowjanya Komatineni i2c-thermtrip: 12939faeba7SSowjanya Komatineni type: object 13039faeba7SSowjanya Komatineni description: 13139faeba7SSowjanya Komatineni On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 13239faeba7SSowjanya Komatineni hardware-triggered thermal reset will be enabled. 13339faeba7SSowjanya Komatineni 13439faeba7SSowjanya Komatineni properties: 13539faeba7SSowjanya Komatineni nvidia,i2c-controller-id: 13639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 13739faeba7SSowjanya Komatineni description: 13839faeba7SSowjanya Komatineni ID of I2C controller to send poweroff command to PMU. 13939faeba7SSowjanya Komatineni Valid values are described in section 9.2.148 14039faeba7SSowjanya Komatineni "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 14139faeba7SSowjanya Komatineni Manual. 14239faeba7SSowjanya Komatineni 14339faeba7SSowjanya Komatineni nvidia,bus-addr: 14439faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 14539faeba7SSowjanya Komatineni description: Bus address of the PMU on the I2C bus. 14639faeba7SSowjanya Komatineni 14739faeba7SSowjanya Komatineni nvidia,reg-addr: 14839faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 14939faeba7SSowjanya Komatineni description: PMU I2C register address to issue poweroff command. 15039faeba7SSowjanya Komatineni 15139faeba7SSowjanya Komatineni nvidia,reg-data: 15239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 15339faeba7SSowjanya Komatineni description: Poweroff command to write to PMU. 15439faeba7SSowjanya Komatineni 15539faeba7SSowjanya Komatineni nvidia,pinmux-id: 15639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 15739faeba7SSowjanya Komatineni description: 15839faeba7SSowjanya Komatineni Pinmux used by the hardware when issuing Poweroff command. 15939faeba7SSowjanya Komatineni Defaults to 0. Valid values are described in section 12.5.2 16039faeba7SSowjanya Komatineni "Pinmux Support" of the Tegra4 Technical Reference Manual. 16139faeba7SSowjanya Komatineni 16239faeba7SSowjanya Komatineni required: 16339faeba7SSowjanya Komatineni - nvidia,i2c-controller-id 16439faeba7SSowjanya Komatineni - nvidia,bus-addr 16539faeba7SSowjanya Komatineni - nvidia,reg-addr 16639faeba7SSowjanya Komatineni - nvidia,reg-data 16739faeba7SSowjanya Komatineni 16839faeba7SSowjanya Komatineni additionalProperties: false 16939faeba7SSowjanya Komatineni 17039faeba7SSowjanya Komatineni powergates: 17139faeba7SSowjanya Komatineni type: object 17239faeba7SSowjanya Komatineni description: | 17339faeba7SSowjanya Komatineni This node contains a hierarchy of power domain nodes, which should 17439faeba7SSowjanya Komatineni match the powergates on the Tegra SoC. Each powergate node 17539faeba7SSowjanya Komatineni represents a power-domain on the Tegra SoC that can be power-gated 17639faeba7SSowjanya Komatineni by the Tegra PMC. 17739faeba7SSowjanya Komatineni Hardware blocks belonging to a power domain should contain 17839faeba7SSowjanya Komatineni "power-domains" property that is a phandle pointing to corresponding 17939faeba7SSowjanya Komatineni powergate node. 18039faeba7SSowjanya Komatineni The name of the powergate node should be one of the below. Note that 18139faeba7SSowjanya Komatineni not every powergate is applicable to all Tegra devices and the following 18239faeba7SSowjanya Komatineni list shows which powergates are applicable to which devices. 18339faeba7SSowjanya Komatineni Please refer to Tegra TRM for mode details on the powergate nodes to 18439faeba7SSowjanya Komatineni use for each power-gate block inside Tegra. 18539faeba7SSowjanya Komatineni Name Description Devices Applicable 18639faeba7SSowjanya Komatineni 3d 3D Graphics Tegra20/114/124/210 18739faeba7SSowjanya Komatineni 3d0 3D Graphics 0 Tegra30 18839faeba7SSowjanya Komatineni 3d1 3D Graphics 1 Tegra30 18939faeba7SSowjanya Komatineni aud Audio Tegra210 19039faeba7SSowjanya Komatineni dfd Debug Tegra210 19139faeba7SSowjanya Komatineni dis Display A Tegra114/124/210 19239faeba7SSowjanya Komatineni disb Display B Tegra114/124/210 19339faeba7SSowjanya Komatineni heg 2D Graphics Tegra30/114/124/210 19439faeba7SSowjanya Komatineni iram Internal RAM Tegra124/210 19539faeba7SSowjanya Komatineni mpe MPEG Encode All 19639faeba7SSowjanya Komatineni nvdec NVIDIA Video Decode Engine Tegra210 19739faeba7SSowjanya Komatineni nvjpg NVIDIA JPEG Engine Tegra210 19839faeba7SSowjanya Komatineni pcie PCIE Tegra20/30/124/210 19939faeba7SSowjanya Komatineni sata SATA Tegra30/124/210 20039faeba7SSowjanya Komatineni sor Display interfaces Tegra124/210 20139faeba7SSowjanya Komatineni ve2 Video Encode Engine 2 Tegra210 20239faeba7SSowjanya Komatineni venc Video Encode Engine All 20339faeba7SSowjanya Komatineni vdec Video Decode Engine Tegra20/30/114/124 20439faeba7SSowjanya Komatineni vic Video Imaging Compositor Tegra124/210 20539faeba7SSowjanya Komatineni xusba USB Partition A Tegra114/124/210 20639faeba7SSowjanya Komatineni xusbb USB Partition B Tegra114/124/210 20739faeba7SSowjanya Komatineni xusbc USB Partition C Tegra114/124/210 20839faeba7SSowjanya Komatineni 20939faeba7SSowjanya Komatineni patternProperties: 21039faeba7SSowjanya Komatineni "^[a-z0-9]+$": 21139faeba7SSowjanya Komatineni type: object 21239faeba7SSowjanya Komatineni 21339faeba7SSowjanya Komatineni patternProperties: 21439faeba7SSowjanya Komatineni clocks: 21539faeba7SSowjanya Komatineni minItems: 1 21639faeba7SSowjanya Komatineni maxItems: 8 21739faeba7SSowjanya Komatineni description: 21839faeba7SSowjanya Komatineni Must contain an entry for each clock required by the PMC 21939faeba7SSowjanya Komatineni for controlling a power-gate. 22039faeba7SSowjanya Komatineni See ../clocks/clock-bindings.txt document for more details. 22139faeba7SSowjanya Komatineni 22239faeba7SSowjanya Komatineni resets: 22339faeba7SSowjanya Komatineni minItems: 1 22439faeba7SSowjanya Komatineni maxItems: 8 22539faeba7SSowjanya Komatineni description: 22639faeba7SSowjanya Komatineni Must contain an entry for each reset required by the PMC 22739faeba7SSowjanya Komatineni for controlling a power-gate. 22839faeba7SSowjanya Komatineni See ../reset/reset.txt for more details. 22939faeba7SSowjanya Komatineni 23039faeba7SSowjanya Komatineni '#power-domain-cells': 23139faeba7SSowjanya Komatineni const: 0 23239faeba7SSowjanya Komatineni description: Must be 0. 23339faeba7SSowjanya Komatineni 23439faeba7SSowjanya Komatineni required: 23539faeba7SSowjanya Komatineni - clocks 23639faeba7SSowjanya Komatineni - resets 23739faeba7SSowjanya Komatineni - '#power-domain-cells' 23839faeba7SSowjanya Komatineni 23939faeba7SSowjanya Komatineni additionalProperties: false 24039faeba7SSowjanya Komatineni 24139faeba7SSowjanya KomatinenipatternProperties: 24239faeba7SSowjanya Komatineni "^[a-f0-9]+-[a-f0-9]+$": 24339faeba7SSowjanya Komatineni type: object 24439faeba7SSowjanya Komatineni description: 24539faeba7SSowjanya Komatineni This is a Pad configuration node. On Tegra SOCs a pad is a set of 24639faeba7SSowjanya Komatineni pins which are configured as a group. The pin grouping is a fixed 24739faeba7SSowjanya Komatineni attribute of the hardware. The PMC can be used to set pad power state 24839faeba7SSowjanya Komatineni and signaling voltage. A pad can be either in active or power down mode. 24939faeba7SSowjanya Komatineni The support for power state and signaling voltage configuration varies 25039faeba7SSowjanya Komatineni depending on the pad in question. 3.3V and 1.8V signaling voltages 25139faeba7SSowjanya Komatineni are supported on pins where software controllable signaling voltage 25239faeba7SSowjanya Komatineni switching is available. 25339faeba7SSowjanya Komatineni 25439faeba7SSowjanya Komatineni The pad configuration state nodes are placed under the pmc node and they 25539faeba7SSowjanya Komatineni are referred to by the pinctrl client properties. For more information 25639faeba7SSowjanya Komatineni see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 25739faeba7SSowjanya Komatineni The pad name should be used as the value of the pins property in pin 25839faeba7SSowjanya Komatineni configuration nodes. 25939faeba7SSowjanya Komatineni 26039faeba7SSowjanya Komatineni The following pads are present on Tegra124 and Tegra132 26139faeba7SSowjanya Komatineni audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 26239faeba7SSowjanya Komatineni hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 26339faeba7SSowjanya Komatineni sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 26439faeba7SSowjanya Komatineni 26539faeba7SSowjanya Komatineni The following pads are present on Tegra210 26639faeba7SSowjanya Komatineni audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 26739faeba7SSowjanya Komatineni debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 26839faeba7SSowjanya Komatineni hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 26939faeba7SSowjanya Komatineni sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 27039faeba7SSowjanya Komatineni 27139faeba7SSowjanya Komatineni properties: 27239faeba7SSowjanya Komatineni pins: 27339faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/string 27439faeba7SSowjanya Komatineni description: Must contain name of the pad(s) to be configured. 27539faeba7SSowjanya Komatineni 27639faeba7SSowjanya Komatineni low-power-enable: 27739faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 27839faeba7SSowjanya Komatineni description: Configure the pad into power down mode. 27939faeba7SSowjanya Komatineni 28039faeba7SSowjanya Komatineni low-power-disable: 28139faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 28239faeba7SSowjanya Komatineni description: Configure the pad into active mode. 28339faeba7SSowjanya Komatineni 28439faeba7SSowjanya Komatineni power-source: 28539faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 28639faeba7SSowjanya Komatineni description: 28739faeba7SSowjanya Komatineni Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 28839faeba7SSowjanya Komatineni TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 28939faeba7SSowjanya Komatineni The values are defined in 29039faeba7SSowjanya Komatineni include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 29139faeba7SSowjanya Komatineni Power state can be configured on all Tegra124 and Tegra132 29239faeba7SSowjanya Komatineni pads. None of the Tegra124 or Tegra132 pads support signaling 29339faeba7SSowjanya Komatineni voltage switching. 29439faeba7SSowjanya Komatineni All of the listed Tegra210 pads except pex-cntrl support power 29539faeba7SSowjanya Komatineni state configuration. Signaling voltage switching is supported 29639faeba7SSowjanya Komatineni on below Tegra210 pads. 29739faeba7SSowjanya Komatineni audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 29839faeba7SSowjanya Komatineni sdmmc3, spi, spi-hv, and uart. 29939faeba7SSowjanya Komatineni 30039faeba7SSowjanya Komatineni required: 30139faeba7SSowjanya Komatineni - pins 30239faeba7SSowjanya Komatineni 30339faeba7SSowjanya Komatineni additionalProperties: false 30439faeba7SSowjanya Komatineni 30539faeba7SSowjanya Komatinenirequired: 30639faeba7SSowjanya Komatineni - compatible 30739faeba7SSowjanya Komatineni - reg 30839faeba7SSowjanya Komatineni - clock-names 30939faeba7SSowjanya Komatineni - clocks 310f85fa319SSowjanya Komatineni - '#clock-cells' 31139faeba7SSowjanya Komatineni 31239faeba7SSowjanya Komatinenidependencies: 31339faeba7SSowjanya Komatineni "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 31439faeba7SSowjanya Komatineni "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 31539faeba7SSowjanya Komatineni "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 31639faeba7SSowjanya Komatineni 31739faeba7SSowjanya Komatineniexamples: 31839faeba7SSowjanya Komatineni - | 31939faeba7SSowjanya Komatineni 32039faeba7SSowjanya Komatineni #include <dt-bindings/clock/tegra210-car.h> 32139faeba7SSowjanya Komatineni #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 322f85fa319SSowjanya Komatineni #include <dt-bindings/soc/tegra-pmc.h> 32339faeba7SSowjanya Komatineni 32439faeba7SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 32539faeba7SSowjanya Komatineni compatible = "nvidia,tegra210-pmc"; 326fba56184SRob Herring reg = <0x7000e400 0x400>; 32739faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 32839faeba7SSowjanya Komatineni clock-names = "pclk", "clk32k_in"; 329f85fa319SSowjanya Komatineni #clock-cells = <1>; 33039faeba7SSowjanya Komatineni 33139faeba7SSowjanya Komatineni nvidia,invert-interrupt; 33239faeba7SSowjanya Komatineni nvidia,suspend-mode = <0>; 33339faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-time = <0>; 33439faeba7SSowjanya Komatineni nvidia,cpu-pwr-off-time = <0>; 33539faeba7SSowjanya Komatineni nvidia,core-pwr-good-time = <4587 3876>; 33639faeba7SSowjanya Komatineni nvidia,core-pwr-off-time = <39065>; 33739faeba7SSowjanya Komatineni nvidia,core-power-req-active-high; 33839faeba7SSowjanya Komatineni nvidia,sys-clock-req-active-high; 33939faeba7SSowjanya Komatineni 34039faeba7SSowjanya Komatineni powergates { 34139faeba7SSowjanya Komatineni pd_audio: aud { 34239faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_APE>, 34339faeba7SSowjanya Komatineni <&tegra_car TEGRA210_CLK_APB2APE>; 34439faeba7SSowjanya Komatineni resets = <&tegra_car 198>; 34539faeba7SSowjanya Komatineni #power-domain-cells = <0>; 34639faeba7SSowjanya Komatineni }; 34739faeba7SSowjanya Komatineni 34839faeba7SSowjanya Komatineni pd_xusbss: xusba { 34939faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 35039faeba7SSowjanya Komatineni resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 35139faeba7SSowjanya Komatineni #power-domain-cells = <0>; 35239faeba7SSowjanya Komatineni }; 35339faeba7SSowjanya Komatineni }; 35439faeba7SSowjanya Komatineni }; 355