1Synaptics SoC Device Tree Bindings
2
3According to https://www.synaptics.com/company/news/conexant-marvell
4Synaptics has acquired the Multimedia Solutions Business of Marvell, so
5berlin SoCs are now Synaptics' SoCs now.
6
7---------------------------------------------------------------
8
9Work in progress statement:
10
11Device tree files and bindings applying to Marvell Berlin SoCs and boards are
12considered "unstable". Any Marvell Berlin device tree binding may change at any
13time. Be sure to use a device tree binary and a kernel image generated from the
14same source tree.
15
16Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
17stable binding/ABI.
18
19---------------------------------------------------------------
20
21Boards with the Synaptics AS370 SoC shall have the following properties:
22  Required root node property:
23    compatible: "syna,as370"
24
25Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
26shall have the following properties:
27
28* Required root node properties:
29compatible: must contain "marvell,berlin"
30
31In addition, the above compatible shall be extended with the specific
32SoC and board used. Currently known SoC compatibles are:
33    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
34    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
35    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
36    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
37    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
38
39* Example:
40
41/ {
42	model = "Sony NSZ-GS7";
43	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
44
45	...
46}
47
48* Marvell Berlin CPU control bindings
49
50CPU control register allows various operations on CPUs, like resetting them
51independently.
52
53Required properties:
54- compatible: should be "marvell,berlin-cpu-ctrl"
55- reg: address and length of the register set
56
57Example:
58
59cpu-ctrl@f7dd0000 {
60	compatible = "marvell,berlin-cpu-ctrl";
61	reg = <0xf7dd0000 0x10000>;
62};
63
64* Marvell Berlin2 chip control binding
65
66Marvell Berlin SoCs have a chip control register set providing several
67individual registers dealing with pinmux, padmux, clock, reset, and secondary
68CPU boot address. Unfortunately, the individual registers are spread among the
69chip control registers, so there should be a single DT node only providing the
70different functions which are described below.
71
72Required properties:
73- compatible:
74	* the first and second values must be:
75		"simple-mfd", "syscon"
76- reg: address and length of following register sets for
77  BG2/BG2CD: chip control register set
78  BG2Q: chip control register set and cpu pll registers
79
80* Marvell Berlin2 system control binding
81
82Marvell Berlin SoCs have a system control register set providing several
83individual registers dealing with pinmux, padmux, and reset.
84
85Required properties:
86- compatible:
87	* the first and second values must be:
88		"simple-mfd", "syscon"
89- reg: address and length of the system control register set
90
91Example:
92
93chip: chip-control@ea0000 {
94	compatible = "simple-mfd", "syscon";
95	reg = <0xea0000 0x400>;
96
97	/* sub-device nodes */
98};
99
100sysctrl: system-controller@d000 {
101	compatible = "simple-mfd", "syscon";
102	reg = <0xd000 0x100>;
103
104	/* sub-device nodes */
105};
106