1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner Memory Bus (MBUS) controller
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13description: |
14  The MBUS controller drives the MBUS that other devices in the SoC
15  will use to perform DMA. It also has a register interface that
16  allows to monitor and control the bandwidth and priorities for
17  masters on that bus.
18
19  Each device having to perform their DMA through the MBUS must have
20  the interconnects and interconnect-names properties set to the MBUS
21  controller and with "dma-mem" as the interconnect name.
22
23properties:
24  "#interconnect-cells":
25    const: 1
26    description:
27      The content of the cell is the MBUS ID.
28
29  compatible:
30    enum:
31      - allwinner,sun5i-a13-mbus
32      - allwinner,sun8i-h3-mbus
33      - allwinner,sun8i-r40-mbus
34      - allwinner,sun50i-a64-mbus
35
36  reg:
37    maxItems: 1
38
39  clocks:
40    maxItems: 1
41
42  dma-ranges:
43    description:
44      See section 2.3.9 of the DeviceTree Specification.
45
46  '#address-cells': true
47
48  '#size-cells': true
49
50required:
51  - "#interconnect-cells"
52  - compatible
53  - reg
54  - clocks
55  - dma-ranges
56
57additionalProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/clock/sun5i-ccu.h>
62
63    mbus: dram-controller@1c01000 {
64        compatible = "allwinner,sun5i-a13-mbus";
65        reg = <0x01c01000 0x1000>;
66        clocks = <&ccu CLK_MBUS>;
67        #address-cells = <1>;
68        #size-cells = <1>;
69        dma-ranges = <0x00000000 0x40000000 0x20000000>;
70        #interconnect-cells = <1>;
71    };
72
73...
74