1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner Memory Bus (MBUS) controller
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13description: |
14  The MBUS controller drives the MBUS that other devices in the SoC
15  will use to perform DMA. It also has a register interface that
16  allows to monitor and control the bandwidth and priorities for
17  masters on that bus.
18
19  Each device having to perform their DMA through the MBUS must have
20  the interconnects and interconnect-names properties set to the MBUS
21  controller and with "dma-mem" as the interconnect name.
22
23properties:
24  "#interconnect-cells":
25    const: 1
26    description:
27      The content of the cell is the MBUS ID.
28
29  compatible:
30    enum:
31      - allwinner,sun5i-a13-mbus
32      - allwinner,sun8i-h3-mbus
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    maxItems: 1
39
40  dma-ranges:
41    description:
42      See section 2.3.9 of the DeviceTree Specification.
43
44required:
45  - "#interconnect-cells"
46  - compatible
47  - reg
48  - clocks
49  - dma-ranges
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/sun5i-ccu.h>
56
57    mbus: dram-controller@1c01000 {
58        compatible = "allwinner,sun5i-a13-mbus";
59        reg = <0x01c01000 0x1000>;
60        clocks = <&ccu CLK_MBUS>;
61        dma-ranges = <0x00000000 0x40000000 0x20000000>;
62        #interconnect-cells = <1>;
63    };
64
65...
66