1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: STMicroelectronics STM32 ML-AHB interconnect
8
9maintainers:
10  - Fabien Dessenne <fabien.dessenne@foss.st.com>
11  - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
12
13description: |
14  These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15  a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
16  parts can be accessed through different addresses (see "RAM aliases" in [1])
17  using different buses (see [2]): balancing the Cortex-M firmware accesses
18  among those ports allows to tune the system performance.
19  [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
20  [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
21
22allOf:
23  - $ref: /schemas/simple-bus.yaml#
24
25properties:
26  compatible:
27    contains:
28      enum:
29        - st,mlahb
30
31  dma-ranges:
32    description: |
33      Describe memory addresses translation between the local CPU and the
34      remote Cortex-M processor. Each memory region, is declared with
35      3 parameters:
36      - param 1: device base address (Cortex-M processor address)
37      - param 2: physical base address (local CPU address)
38      - param 3: size of the memory region.
39    maxItems: 3
40
41  '#address-cells':
42    const: 1
43
44  '#size-cells':
45    const: 1
46
47required:
48  - compatible
49  - '#address-cells'
50  - '#size-cells'
51  - dma-ranges
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    mlahb: ahb@38000000 {
58      compatible = "st,mlahb", "simple-bus";
59      #address-cells = <1>;
60      #size-cells = <1>;
61      reg = <0x10000000 0x40000>;
62      ranges;
63      dma-ranges = <0x00000000 0x38000000 0x10000>,
64                   <0x10000000 0x10000000 0x60000>,
65                   <0x30000000 0x30000000 0x60000>;
66
67      m4_rproc: m4@10000000 {
68       reg = <0x10000000 0x40000>;
69      };
70    };
71
72...
73