1*a8fbe144SMao Jinlong# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2*a8fbe144SMao Jinlong# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*a8fbe144SMao Jinlong%YAML 1.2 4*a8fbe144SMao Jinlong--- 5*a8fbe144SMao Jinlong$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml# 6*a8fbe144SMao Jinlong$schema: http://devicetree.org/meta-schemas/core.yaml# 7*a8fbe144SMao Jinlong 8*a8fbe144SMao Jinlongtitle: Trace, Profiling and Diagnostics Aggregator - TPDA 9*a8fbe144SMao Jinlong 10*a8fbe144SMao Jinlongdescription: | 11*a8fbe144SMao Jinlong TPDAs are responsible for packetization and timestamping of data sets 12*a8fbe144SMao Jinlong utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or 13*a8fbe144SMao Jinlong more attached TPDM and pushing the resultant (packetized) data out a 14*a8fbe144SMao Jinlong master ATB interface. Performing an arbitrated ATB interleaving (funneling) 15*a8fbe144SMao Jinlong task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). 16*a8fbe144SMao Jinlong 17*a8fbe144SMao Jinlong There is no strict binding between TPDM and TPDA. TPDA can have multiple 18*a8fbe144SMao Jinlong TPDMs connect to it. But There must be only one TPDA in the path from the 19*a8fbe144SMao Jinlong TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or 20*a8fbe144SMao Jinlong connect to funnel which will connect to TPDA's inport. 21*a8fbe144SMao Jinlong 22*a8fbe144SMao Jinlong We can use the commands are similar to the below to validate TPDMs. 23*a8fbe144SMao Jinlong Enable coresight sink first. 24*a8fbe144SMao Jinlong 25*a8fbe144SMao Jinlong echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink 26*a8fbe144SMao Jinlong echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source 27*a8fbe144SMao Jinlong echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test 28*a8fbe144SMao Jinlong echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test 29*a8fbe144SMao Jinlong 30*a8fbe144SMao Jinlong The test data will be collected in the coresight sink which is enabled. 31*a8fbe144SMao Jinlong If rwp register of the sink is keeping updating when do integration_test 32*a8fbe144SMao Jinlong (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM 33*a8fbe144SMao Jinlong to sink. 34*a8fbe144SMao Jinlong 35*a8fbe144SMao Jinlongmaintainers: 36*a8fbe144SMao Jinlong - Mao Jinlong <quic_jinlmao@quicinc.com> 37*a8fbe144SMao Jinlong - Tao Zhang <quic_taozha@quicinc.com> 38*a8fbe144SMao Jinlong 39*a8fbe144SMao Jinlong# Need a custom select here or 'arm,primecell' will match on lots of nodes 40*a8fbe144SMao Jinlongselect: 41*a8fbe144SMao Jinlong properties: 42*a8fbe144SMao Jinlong compatible: 43*a8fbe144SMao Jinlong contains: 44*a8fbe144SMao Jinlong enum: 45*a8fbe144SMao Jinlong - qcom,coresight-tpda 46*a8fbe144SMao Jinlong required: 47*a8fbe144SMao Jinlong - compatible 48*a8fbe144SMao Jinlong 49*a8fbe144SMao Jinlongproperties: 50*a8fbe144SMao Jinlong $nodename: 51*a8fbe144SMao Jinlong pattern: "^tpda(@[0-9a-f]+)$" 52*a8fbe144SMao Jinlong compatible: 53*a8fbe144SMao Jinlong items: 54*a8fbe144SMao Jinlong - const: qcom,coresight-tpda 55*a8fbe144SMao Jinlong - const: arm,primecell 56*a8fbe144SMao Jinlong 57*a8fbe144SMao Jinlong reg: 58*a8fbe144SMao Jinlong minItems: 1 59*a8fbe144SMao Jinlong maxItems: 2 60*a8fbe144SMao Jinlong 61*a8fbe144SMao Jinlong clocks: 62*a8fbe144SMao Jinlong maxItems: 1 63*a8fbe144SMao Jinlong 64*a8fbe144SMao Jinlong clock-names: 65*a8fbe144SMao Jinlong items: 66*a8fbe144SMao Jinlong - const: apb_pclk 67*a8fbe144SMao Jinlong 68*a8fbe144SMao Jinlong in-ports: 69*a8fbe144SMao Jinlong type: object 70*a8fbe144SMao Jinlong description: | 71*a8fbe144SMao Jinlong Input connections from TPDM to TPDA 72*a8fbe144SMao Jinlong $ref: /schemas/graph.yaml#/properties/ports 73*a8fbe144SMao Jinlong 74*a8fbe144SMao Jinlong out-ports: 75*a8fbe144SMao Jinlong type: object 76*a8fbe144SMao Jinlong description: | 77*a8fbe144SMao Jinlong Output connections from the TPDA to legacy CoreSight trace bus. 78*a8fbe144SMao Jinlong $ref: /schemas/graph.yaml#/properties/ports 79*a8fbe144SMao Jinlong 80*a8fbe144SMao Jinlong properties: 81*a8fbe144SMao Jinlong port: 82*a8fbe144SMao Jinlong description: 83*a8fbe144SMao Jinlong Output connection from the TPDA to legacy CoreSight Trace bus. 84*a8fbe144SMao Jinlong $ref: /schemas/graph.yaml#/properties/port 85*a8fbe144SMao Jinlong 86*a8fbe144SMao Jinlongrequired: 87*a8fbe144SMao Jinlong - compatible 88*a8fbe144SMao Jinlong - reg 89*a8fbe144SMao Jinlong - clocks 90*a8fbe144SMao Jinlong - clock-names 91*a8fbe144SMao Jinlong - in-ports 92*a8fbe144SMao Jinlong - out-ports 93*a8fbe144SMao Jinlong 94*a8fbe144SMao JinlongadditionalProperties: false 95*a8fbe144SMao Jinlong 96*a8fbe144SMao Jinlongexamples: 97*a8fbe144SMao Jinlong # minimum tpda definition. 98*a8fbe144SMao Jinlong - | 99*a8fbe144SMao Jinlong tpda@6004000 { 100*a8fbe144SMao Jinlong compatible = "qcom,coresight-tpda", "arm,primecell"; 101*a8fbe144SMao Jinlong reg = <0x6004000 0x1000>; 102*a8fbe144SMao Jinlong 103*a8fbe144SMao Jinlong clocks = <&aoss_qmp>; 104*a8fbe144SMao Jinlong clock-names = "apb_pclk"; 105*a8fbe144SMao Jinlong 106*a8fbe144SMao Jinlong in-ports { 107*a8fbe144SMao Jinlong #address-cells = <1>; 108*a8fbe144SMao Jinlong #size-cells = <0>; 109*a8fbe144SMao Jinlong 110*a8fbe144SMao Jinlong port@0 { 111*a8fbe144SMao Jinlong reg = <0>; 112*a8fbe144SMao Jinlong tpda_qdss_0_in_tpdm_dcc: endpoint { 113*a8fbe144SMao Jinlong remote-endpoint = 114*a8fbe144SMao Jinlong <&tpdm_dcc_out_tpda_qdss_0>; 115*a8fbe144SMao Jinlong }; 116*a8fbe144SMao Jinlong }; 117*a8fbe144SMao Jinlong }; 118*a8fbe144SMao Jinlong 119*a8fbe144SMao Jinlong out-ports { 120*a8fbe144SMao Jinlong port { 121*a8fbe144SMao Jinlong tpda_qdss_out_funnel_in0: endpoint { 122*a8fbe144SMao Jinlong remote-endpoint = 123*a8fbe144SMao Jinlong <&funnel_in0_in_tpda_qdss>; 124*a8fbe144SMao Jinlong }; 125*a8fbe144SMao Jinlong }; 126*a8fbe144SMao Jinlong }; 127*a8fbe144SMao Jinlong }; 128*a8fbe144SMao Jinlong 129*a8fbe144SMao Jinlong... 130