1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Performance Monitor Units
8
9maintainers:
10  - Mark Rutland <mark.rutland@arm.com>
11  - Will Deacon <will.deacon@arm.com>
12
13description: |+
14  ARM cores often have a PMU for counting cpu and cache events like cache misses
15  and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16  representation in the device tree should be done as under:-
17
18properties:
19  compatible:
20    items:
21      - enum:
22          - apm,potenza-pmu
23          - arm,armv8-pmuv3
24          - arm,cortex-a73-pmu
25          - arm,cortex-a72-pmu
26          - arm,cortex-a57-pmu
27          - arm,cortex-a53-pmu
28          - arm,cortex-a35-pmu
29          - arm,cortex-a17-pmu
30          - arm,cortex-a15-pmu
31          - arm,cortex-a12-pmu
32          - arm,cortex-a9-pmu
33          - arm,cortex-a8-pmu
34          - arm,cortex-a7-pmu
35          - arm,cortex-a5-pmu
36          - arm,arm11mpcore-pmu
37          - arm,arm1176-pmu
38          - arm,arm1136-pmu
39          - brcm,vulcan-pmu
40          - cavium,thunder-pmu
41          - qcom,scorpion-pmu
42          - qcom,scorpion-mp-pmu
43          - qcom,krait-pmu
44
45  interrupts:
46    # Don't know how many CPUs, so no constraints to specify
47    description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
48
49  interrupt-affinity:
50    $ref: /schemas/types.yaml#/definitions/phandle-array
51    description:
52      When using SPIs, specifies a list of phandles to CPU
53      nodes corresponding directly to the affinity of
54      the SPIs listed in the interrupts property.
55
56      When using a PPI, specifies a list of phandles to CPU
57      nodes corresponding to the set of CPUs which have
58      a PMU of this type signalling the PPI listed in the
59      interrupts property, unless this is already specified
60      by the PPI interrupt specifier itself (in which case
61      the interrupt-affinity property shouldn't be present).
62
63      This property should be present when there is more than
64      a single SPI.
65
66  qcom,no-pc-write:
67    type: boolean
68    description:
69      Indicates that this PMU doesn't support the 0xc and 0xd events.
70
71  secure-reg-access:
72    type: boolean
73    description:
74      Indicates that the ARMv7 Secure Debug Enable Register
75      (SDER) is accessible. This will cause the driver to do
76      any setup required that is only possible in ARMv7 secure
77      state. If not present the ARMv7 SDER will not be touched,
78      which means the PMU may fail to operate unless external
79      code (bootloader or security monitor) has performed the
80      appropriate initialisation. Note that this property is
81      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
82      in Non-secure state.
83
84required:
85  - compatible
86
87...
88