1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Performance Monitor Units
8
9maintainers:
10  - Mark Rutland <mark.rutland@arm.com>
11  - Will Deacon <will.deacon@arm.com>
12
13description: |+
14  ARM cores often have a PMU for counting cpu and cache events like cache misses
15  and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16  representation in the device tree should be done as under:-
17
18properties:
19  compatible:
20    items:
21      - enum:
22          - apm,potenza-pmu
23          - arm,armv8-pmuv3 # Only for s/w models
24          - arm,arm1136-pmu
25          - arm,arm1176-pmu
26          - arm,arm11mpcore-pmu
27          - arm,cortex-a5-pmu
28          - arm,cortex-a7-pmu
29          - arm,cortex-a8-pmu
30          - arm,cortex-a9-pmu
31          - arm,cortex-a12-pmu
32          - arm,cortex-a15-pmu
33          - arm,cortex-a17-pmu
34          - arm,cortex-a32-pmu
35          - arm,cortex-a34-pmu
36          - arm,cortex-a35-pmu
37          - arm,cortex-a53-pmu
38          - arm,cortex-a55-pmu
39          - arm,cortex-a57-pmu
40          - arm,cortex-a65-pmu
41          - arm,cortex-a72-pmu
42          - arm,cortex-a73-pmu
43          - arm,cortex-a75-pmu
44          - arm,cortex-a76-pmu
45          - arm,cortex-a77-pmu
46          - arm,cortex-a78-pmu
47          - arm,cortex-a510-pmu
48          - arm,cortex-a710-pmu
49          - arm,cortex-x1-pmu
50          - arm,cortex-x2-pmu
51          - arm,neoverse-e1-pmu
52          - arm,neoverse-n1-pmu
53          - arm,neoverse-n2-pmu
54          - arm,neoverse-v1-pmu
55          - brcm,vulcan-pmu
56          - cavium,thunder-pmu
57          - nvidia,denver-pmu
58          - nvidia,carmel-pmu
59          - qcom,krait-pmu
60          - qcom,scorpion-pmu
61          - qcom,scorpion-mp-pmu
62
63  interrupts:
64    # Don't know how many CPUs, so no constraints to specify
65    description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
66
67  interrupt-affinity:
68    $ref: /schemas/types.yaml#/definitions/phandle-array
69    description:
70      When using SPIs, specifies a list of phandles to CPU
71      nodes corresponding directly to the affinity of
72      the SPIs listed in the interrupts property.
73
74      When using a PPI, specifies a list of phandles to CPU
75      nodes corresponding to the set of CPUs which have
76      a PMU of this type signalling the PPI listed in the
77      interrupts property, unless this is already specified
78      by the PPI interrupt specifier itself (in which case
79      the interrupt-affinity property shouldn't be present).
80
81      This property should be present when there is more than
82      a single SPI.
83
84  qcom,no-pc-write:
85    type: boolean
86    description:
87      Indicates that this PMU doesn't support the 0xc and 0xd events.
88
89  secure-reg-access:
90    type: boolean
91    description:
92      Indicates that the ARMv7 Secure Debug Enable Register
93      (SDER) is accessible. This will cause the driver to do
94      any setup required that is only possible in ARMv7 secure
95      state. If not present the ARMv7 SDER will not be touched,
96      which means the PMU may fail to operate unless external
97      code (bootloader or security monitor) has performed the
98      appropriate initialisation. Note that this property is
99      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
100      in Non-secure state.
101
102required:
103  - compatible
104
105additionalProperties: false
106
107...
108