196ca848eSSricharan RSome socs have a large number of interrupts requests to service 296ca848eSSricharan Rthe needs of its many peripherals and subsystems. All of the 396ca848eSSricharan Rinterrupt lines from the subsystems are not needed at the same 496ca848eSSricharan Rtime, so they have to be muxed to the irq-controller appropriately. 596ca848eSSricharan RIn such places a interrupt controllers are preceded by an CROSSBAR 696ca848eSSricharan Rthat provides flexibility in muxing the device requests to the controller 796ca848eSSricharan Rinputs. 896ca848eSSricharan R 996ca848eSSricharan RRequired properties: 1096ca848eSSricharan R- compatible : Should be "ti,irq-crossbar" 1196ca848eSSricharan R- reg: Base address and the size of the crossbar registers. 1296ca848eSSricharan R- ti,max-irqs: Total number of irqs available at the interrupt controller. 1396ca848eSSricharan R- ti,reg-size: Size of a individual register in bytes. Every individual 1496ca848eSSricharan R register is assumed to be of same size. Valid sizes are 1, 2, 4. 1596ca848eSSricharan R- ti,irqs-reserved: List of the reserved irq lines that are not muxed using 1696ca848eSSricharan R crossbar. These interrupt lines are reserved in the soc, 1796ca848eSSricharan R so crossbar bar driver should not consider them as free 1896ca848eSSricharan R lines. 1996ca848eSSricharan R 2064e0f8baSNishanth MenonOptional properties: 2164e0f8baSNishanth Menon- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for 2264e0f8baSNishanth Menon SOC-specific hard-wiring of those irqs which unexpectedly bypasses the 2364e0f8baSNishanth Menon crossbar. These irqs have a crossbar register, but still cannot be used. 2464e0f8baSNishanth Menon 25a35057d1SNishanth Menon- ti,irqs-safe-map: integer which maps to a safe configuration to use 26a35057d1SNishanth Menon when the interrupt controller irq is unused (when not provided, default is 0) 27a35057d1SNishanth Menon 2896ca848eSSricharan RExamples: 2996ca848eSSricharan R crossbar_mpu: @4a020000 { 3096ca848eSSricharan R compatible = "ti,irq-crossbar"; 3196ca848eSSricharan R reg = <0x4a002a48 0x130>; 3296ca848eSSricharan R ti,max-irqs = <160>; 3396ca848eSSricharan R ti,reg-size = <2>; 3496ca848eSSricharan R ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; 3564e0f8baSNishanth Menon ti,irqs-skip = <10 133 139 140>; 3696ca848eSSricharan R }; 37