1QCOM Idle States for cpuidle driver
2
3ARM provides idle-state node to define the cpuidle states, as defined in [1].
4cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5states. Idle states have different enter/exit latency and residency values.
6The idle states supported by the QCOM SoC are defined as -
7
8    * Standby
9    * Retention
10    * Standalone Power Collapse (Standalone PC or SPC)
11    * Power Collapse (PC)
12
13Standby: Standby does a little more in addition to architectural clock gating.
14When the WFI instruction is executed the ARM core would gate its internal
15clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
16trigger to execute the SPM state machine. The SPM state machine waits for the
17interrupt to trigger the core back in to active. This triggers the cache
18hierarchy to enter standby states, when all cpus are idle. An interrupt brings
19the SPM state machine out of its wait, the next step is to ensure that the
20cache hierarchy is also out of standby, and then the cpu is allowed to resume
21execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
22driver and is not defined in the DT. The SPM state machine should be
23configured to execute this state by default and after executing every other
24state below.
25
26Retention: Retention is a low power state where the core is clock gated and
27the memory and the registers associated with the core are retained. The
28voltage may be reduced to the minimum value needed to keep the processor
29registers active. The SPM should be configured to execute the retention
30sequence and would wait for interrupt, before restoring the cpu to execution
31state. Retention may have a slightly higher latency than Standby.
32
33Standalone PC: A cpu can power down and warmboot if there is a sufficient time
34between the time it enters idle and the next known wake up. SPC mode is used
35to indicate a core entering a power down state without consulting any other
36cpu or the system resources. This helps save power only on that core.  The SPM
37sequence for this idle state is programmed to power down the supply to the
38core, wait for the interrupt, restore power to the core, and ensure the
39system state including cache hierarchy is ready before allowing core to
40resume. Applying power and resetting the core causes the core to warmboot
41back into Elevation Level (EL) which trampolines the control back to the
42kernel. Entering a power down state for the cpu, needs to be done by trapping
43into a EL. Failing to do so, would result in a crash enforced by the warm boot
44code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
45be flushed in s/w, before powering down the core.
46
47Power Collapse: This state is similar to the SPC mode, but distinguishes
48itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49modes. In a hierarchical power domain SoC, this means L2 and other caches can
50be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
51voltages reduced, provided all cpus enter this state.  Since the span of low
52power modes possible at this state is vast, the exit latency and the residency
53of this low power mode would be considered high even though at a cpu level,
54this essentially is cpu power down. The SPM in this state also may handshake
55with the Resource power manager (RPM) processor in the SoC to indicate a
56complete application processor subsystem shut down.
57
58The idle-state for QCOM SoCs are distinguished by the compatible property of
59the idle-states device node.
60
61The devicetree representation of the idle state should be -
62
63Required properties:
64
65- compatible: Must be one of -
66			"qcom,idle-state-ret",
67			"qcom,idle-state-spc",
68			"qcom,idle-state-pc",
69		and "arm,idle-state".
70
71Other required and optional properties are specified in [1].
72
73Example:
74
75	idle-states {
76		CPU_SPC: spc {
77			compatible = "qcom,idle-state-spc", "arm,idle-state";
78			entry-latency-us = <150>;
79			exit-latency-us = <200>;
80			min-residency-us = <2000>;
81		};
82	};
83
84[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
85