1808ecf4aSSean WangMediaTek PCIESYS controller 2808ecf4aSSean Wang============================ 3808ecf4aSSean Wang 4808ecf4aSSean WangThe MediaTek PCIESYS controller provides various clocks to the system. 5808ecf4aSSean Wang 6808ecf4aSSean WangRequired Properties: 7808ecf4aSSean Wang 8808ecf4aSSean Wang- compatible: Should be: 9808ecf4aSSean Wang - "mediatek,mt7622-pciesys", "syscon" 10808ecf4aSSean Wang- #clock-cells: Must be 1 112c97fa22SSean Wang- #reset-cells: Must be 1 12808ecf4aSSean Wang 13808ecf4aSSean WangThe PCIESYS controller uses the common clk binding from 14808ecf4aSSean WangDocumentation/devicetree/bindings/clock/clock-bindings.txt 15808ecf4aSSean WangThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 16808ecf4aSSean Wang 17808ecf4aSSean WangExample: 18808ecf4aSSean Wang 19808ecf4aSSean Wangpciesys: pciesys@1a100800 { 20808ecf4aSSean Wang compatible = "mediatek,mt7622-pciesys", "syscon"; 21808ecf4aSSean Wang reg = <0 0x1a100800 0 0x1000>; 22808ecf4aSSean Wang #clock-cells = <1>; 232c97fa22SSean Wang #reset-cells = <1>; 24808ecf4aSSean Wang}; 25