1808ecf4aSSean WangMediaTek PCIESYS controller 2808ecf4aSSean Wang============================ 3808ecf4aSSean Wang 4808ecf4aSSean WangThe MediaTek PCIESYS controller provides various clocks to the system. 5808ecf4aSSean Wang 6808ecf4aSSean WangRequired Properties: 7808ecf4aSSean Wang 8808ecf4aSSean Wang- compatible: Should be: 9808ecf4aSSean Wang - "mediatek,mt7622-pciesys", "syscon" 100cd41af0SRyder Lee - "mediatek,mt7629-pciesys", "syscon" 11808ecf4aSSean Wang- #clock-cells: Must be 1 122c97fa22SSean Wang- #reset-cells: Must be 1 13808ecf4aSSean Wang 14808ecf4aSSean WangThe PCIESYS controller uses the common clk binding from 15808ecf4aSSean WangDocumentation/devicetree/bindings/clock/clock-bindings.txt 16808ecf4aSSean WangThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 17808ecf4aSSean Wang 18808ecf4aSSean WangExample: 19808ecf4aSSean Wang 20808ecf4aSSean Wangpciesys: pciesys@1a100800 { 21808ecf4aSSean Wang compatible = "mediatek,mt7622-pciesys", "syscon"; 22808ecf4aSSean Wang reg = <0 0x1a100800 0 0x1000>; 23808ecf4aSSean Wang #clock-cells = <1>; 242c97fa22SSean Wang #reset-cells = <1>; 25808ecf4aSSean Wang}; 26