134d3ed3bSChun-Jie Chen# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 234d3ed3bSChun-Jie Chen%YAML 1.2 334d3ed3bSChun-Jie Chen--- 434d3ed3bSChun-Jie Chen$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#" 534d3ed3bSChun-Jie Chen$schema: "http://devicetree.org/meta-schemas/core.yaml#" 634d3ed3bSChun-Jie Chen 734d3ed3bSChun-Jie Chentitle: MediaTek System Clock Controller for MT8195 834d3ed3bSChun-Jie Chen 934d3ed3bSChun-Jie Chenmaintainers: 1034d3ed3bSChun-Jie Chen - Chun-Jie Chen <chun-jie.chen@mediatek.com> 1134d3ed3bSChun-Jie Chen 1234d3ed3bSChun-Jie Chendescription: 1334d3ed3bSChun-Jie Chen The clock architecture in Mediatek like below 1434d3ed3bSChun-Jie Chen PLLs --> 1534d3ed3bSChun-Jie Chen dividers --> 1634d3ed3bSChun-Jie Chen muxes 1734d3ed3bSChun-Jie Chen --> 1834d3ed3bSChun-Jie Chen clock gate 1934d3ed3bSChun-Jie Chen 2034d3ed3bSChun-Jie Chen The apmixedsys provides most of PLLs which generated from SoC 26m. 2134d3ed3bSChun-Jie Chen The topckgen provides dividers and muxes which provide the clock source to other IP blocks. 2234d3ed3bSChun-Jie Chen The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. 2334d3ed3bSChun-Jie Chen 2434d3ed3bSChun-Jie Chenproperties: 2534d3ed3bSChun-Jie Chen compatible: 2634d3ed3bSChun-Jie Chen items: 2734d3ed3bSChun-Jie Chen - enum: 2834d3ed3bSChun-Jie Chen - mediatek,mt8195-topckgen 2934d3ed3bSChun-Jie Chen - mediatek,mt8195-infracfg_ao 3034d3ed3bSChun-Jie Chen - mediatek,mt8195-apmixedsys 3134d3ed3bSChun-Jie Chen - mediatek,mt8195-pericfg_ao 3234d3ed3bSChun-Jie Chen - const: syscon 3334d3ed3bSChun-Jie Chen 3434d3ed3bSChun-Jie Chen reg: 3534d3ed3bSChun-Jie Chen maxItems: 1 3634d3ed3bSChun-Jie Chen 3734d3ed3bSChun-Jie Chen '#clock-cells': 3834d3ed3bSChun-Jie Chen const: 1 3934d3ed3bSChun-Jie Chen 40*4d352eb9SRex-BC Chen '#reset-cells': 41*4d352eb9SRex-BC Chen const: 1 42*4d352eb9SRex-BC Chen 4334d3ed3bSChun-Jie Chenrequired: 4434d3ed3bSChun-Jie Chen - compatible 4534d3ed3bSChun-Jie Chen - reg 4634d3ed3bSChun-Jie Chen 4734d3ed3bSChun-Jie ChenadditionalProperties: false 4834d3ed3bSChun-Jie Chen 4934d3ed3bSChun-Jie Chenexamples: 5034d3ed3bSChun-Jie Chen - | 5134d3ed3bSChun-Jie Chen topckgen: syscon@10000000 { 5234d3ed3bSChun-Jie Chen compatible = "mediatek,mt8195-topckgen", "syscon"; 5334d3ed3bSChun-Jie Chen reg = <0x10000000 0x1000>; 5434d3ed3bSChun-Jie Chen #clock-cells = <1>; 5534d3ed3bSChun-Jie Chen }; 5634d3ed3bSChun-Jie Chen 5734d3ed3bSChun-Jie Chen - | 5834d3ed3bSChun-Jie Chen infracfg_ao: syscon@10001000 { 5934d3ed3bSChun-Jie Chen compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 6034d3ed3bSChun-Jie Chen reg = <0x10001000 0x1000>; 6134d3ed3bSChun-Jie Chen #clock-cells = <1>; 6234d3ed3bSChun-Jie Chen }; 6334d3ed3bSChun-Jie Chen 6434d3ed3bSChun-Jie Chen - | 6534d3ed3bSChun-Jie Chen apmixedsys: syscon@1000c000 { 6634d3ed3bSChun-Jie Chen compatible = "mediatek,mt8195-apmixedsys", "syscon"; 6734d3ed3bSChun-Jie Chen reg = <0x1000c000 0x1000>; 6834d3ed3bSChun-Jie Chen #clock-cells = <1>; 6934d3ed3bSChun-Jie Chen }; 7034d3ed3bSChun-Jie Chen 7134d3ed3bSChun-Jie Chen - | 7234d3ed3bSChun-Jie Chen pericfg_ao: syscon@11003000 { 7334d3ed3bSChun-Jie Chen compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 7434d3ed3bSChun-Jie Chen reg = <0x11003000 0x1000>; 7534d3ed3bSChun-Jie Chen #clock-cells = <1>; 7634d3ed3bSChun-Jie Chen }; 77