1*4a803990SChun-Jie Chen# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4a803990SChun-Jie Chen%YAML 1.2 3*4a803990SChun-Jie Chen--- 4*4a803990SChun-Jie Chen$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#" 5*4a803990SChun-Jie Chen$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4a803990SChun-Jie Chen 7*4a803990SChun-Jie Chentitle: MediaTek System Clock Controller for MT8192 8*4a803990SChun-Jie Chen 9*4a803990SChun-Jie Chenmaintainers: 10*4a803990SChun-Jie Chen - Chun-Jie Chen <chun-jie.chen@mediatek.com> 11*4a803990SChun-Jie Chen 12*4a803990SChun-Jie Chendescription: 13*4a803990SChun-Jie Chen The Mediatek system clock controller provides various clocks and system configuration 14*4a803990SChun-Jie Chen like reset and bus protection on MT8192. 15*4a803990SChun-Jie Chen 16*4a803990SChun-Jie Chenproperties: 17*4a803990SChun-Jie Chen compatible: 18*4a803990SChun-Jie Chen items: 19*4a803990SChun-Jie Chen - enum: 20*4a803990SChun-Jie Chen - mediatek,mt8192-topckgen 21*4a803990SChun-Jie Chen - mediatek,mt8192-infracfg 22*4a803990SChun-Jie Chen - mediatek,mt8192-pericfg 23*4a803990SChun-Jie Chen - mediatek,mt8192-apmixedsys 24*4a803990SChun-Jie Chen - const: syscon 25*4a803990SChun-Jie Chen 26*4a803990SChun-Jie Chen reg: 27*4a803990SChun-Jie Chen maxItems: 1 28*4a803990SChun-Jie Chen 29*4a803990SChun-Jie Chen '#clock-cells': 30*4a803990SChun-Jie Chen const: 1 31*4a803990SChun-Jie Chen 32*4a803990SChun-Jie Chenrequired: 33*4a803990SChun-Jie Chen - compatible 34*4a803990SChun-Jie Chen - reg 35*4a803990SChun-Jie Chen 36*4a803990SChun-Jie ChenadditionalProperties: false 37*4a803990SChun-Jie Chen 38*4a803990SChun-Jie Chenexamples: 39*4a803990SChun-Jie Chen - | 40*4a803990SChun-Jie Chen topckgen: syscon@10000000 { 41*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 42*4a803990SChun-Jie Chen reg = <0x10000000 0x1000>; 43*4a803990SChun-Jie Chen #clock-cells = <1>; 44*4a803990SChun-Jie Chen }; 45*4a803990SChun-Jie Chen 46*4a803990SChun-Jie Chen - | 47*4a803990SChun-Jie Chen infracfg: syscon@10001000 { 48*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 49*4a803990SChun-Jie Chen reg = <0x10001000 0x1000>; 50*4a803990SChun-Jie Chen #clock-cells = <1>; 51*4a803990SChun-Jie Chen }; 52*4a803990SChun-Jie Chen 53*4a803990SChun-Jie Chen - | 54*4a803990SChun-Jie Chen pericfg: syscon@10003000 { 55*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 56*4a803990SChun-Jie Chen reg = <0x10003000 0x1000>; 57*4a803990SChun-Jie Chen #clock-cells = <1>; 58*4a803990SChun-Jie Chen }; 59*4a803990SChun-Jie Chen 60*4a803990SChun-Jie Chen - | 61*4a803990SChun-Jie Chen apmixedsys: syscon@1000c000 { 62*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 63*4a803990SChun-Jie Chen reg = <0x1000c000 0x1000>; 64*4a803990SChun-Jie Chen #clock-cells = <1>; 65*4a803990SChun-Jie Chen }; 66