1*4a803990SChun-Jie Chen# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4a803990SChun-Jie Chen%YAML 1.2 3*4a803990SChun-Jie Chen--- 4*4a803990SChun-Jie Chen$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#" 5*4a803990SChun-Jie Chen$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4a803990SChun-Jie Chen 7*4a803990SChun-Jie Chentitle: MediaTek Functional Clock Controller for MT8192 8*4a803990SChun-Jie Chen 9*4a803990SChun-Jie Chenmaintainers: 10*4a803990SChun-Jie Chen - Chun-Jie Chen <chun-jie.chen@mediatek.com> 11*4a803990SChun-Jie Chen 12*4a803990SChun-Jie Chendescription: 13*4a803990SChun-Jie Chen The Mediatek functional clock controller provides various clocks on MT8192. 14*4a803990SChun-Jie Chen 15*4a803990SChun-Jie Chenproperties: 16*4a803990SChun-Jie Chen compatible: 17*4a803990SChun-Jie Chen items: 18*4a803990SChun-Jie Chen - enum: 19*4a803990SChun-Jie Chen - mediatek,mt8192-scp_adsp 20*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_c 21*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_e 22*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_s 23*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_ws 24*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_w 25*4a803990SChun-Jie Chen - mediatek,mt8192-imp_iic_wrap_n 26*4a803990SChun-Jie Chen - mediatek,mt8192-msdc_top 27*4a803990SChun-Jie Chen - mediatek,mt8192-msdc 28*4a803990SChun-Jie Chen - mediatek,mt8192-mfgcfg 29*4a803990SChun-Jie Chen - mediatek,mt8192-imgsys 30*4a803990SChun-Jie Chen - mediatek,mt8192-imgsys2 31*4a803990SChun-Jie Chen - mediatek,mt8192-vdecsys_soc 32*4a803990SChun-Jie Chen - mediatek,mt8192-vdecsys 33*4a803990SChun-Jie Chen - mediatek,mt8192-vencsys 34*4a803990SChun-Jie Chen - mediatek,mt8192-camsys 35*4a803990SChun-Jie Chen - mediatek,mt8192-camsys_rawa 36*4a803990SChun-Jie Chen - mediatek,mt8192-camsys_rawb 37*4a803990SChun-Jie Chen - mediatek,mt8192-camsys_rawc 38*4a803990SChun-Jie Chen - mediatek,mt8192-ipesys 39*4a803990SChun-Jie Chen - mediatek,mt8192-mdpsys 40*4a803990SChun-Jie Chen 41*4a803990SChun-Jie Chen reg: 42*4a803990SChun-Jie Chen maxItems: 1 43*4a803990SChun-Jie Chen 44*4a803990SChun-Jie Chen '#clock-cells': 45*4a803990SChun-Jie Chen const: 1 46*4a803990SChun-Jie Chen 47*4a803990SChun-Jie Chenrequired: 48*4a803990SChun-Jie Chen - compatible 49*4a803990SChun-Jie Chen - reg 50*4a803990SChun-Jie Chen 51*4a803990SChun-Jie ChenadditionalProperties: false 52*4a803990SChun-Jie Chen 53*4a803990SChun-Jie Chenexamples: 54*4a803990SChun-Jie Chen - | 55*4a803990SChun-Jie Chen scp_adsp: clock-controller@10720000 { 56*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 57*4a803990SChun-Jie Chen reg = <0x10720000 0x1000>; 58*4a803990SChun-Jie Chen #clock-cells = <1>; 59*4a803990SChun-Jie Chen }; 60*4a803990SChun-Jie Chen 61*4a803990SChun-Jie Chen - | 62*4a803990SChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 63*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 64*4a803990SChun-Jie Chen reg = <0x11007000 0x1000>; 65*4a803990SChun-Jie Chen #clock-cells = <1>; 66*4a803990SChun-Jie Chen }; 67*4a803990SChun-Jie Chen 68*4a803990SChun-Jie Chen - | 69*4a803990SChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 70*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 71*4a803990SChun-Jie Chen reg = <0x11cb1000 0x1000>; 72*4a803990SChun-Jie Chen #clock-cells = <1>; 73*4a803990SChun-Jie Chen }; 74*4a803990SChun-Jie Chen 75*4a803990SChun-Jie Chen - | 76*4a803990SChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 77*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 78*4a803990SChun-Jie Chen reg = <0x11d03000 0x1000>; 79*4a803990SChun-Jie Chen #clock-cells = <1>; 80*4a803990SChun-Jie Chen }; 81*4a803990SChun-Jie Chen 82*4a803990SChun-Jie Chen - | 83*4a803990SChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 84*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 85*4a803990SChun-Jie Chen reg = <0x11d23000 0x1000>; 86*4a803990SChun-Jie Chen #clock-cells = <1>; 87*4a803990SChun-Jie Chen }; 88*4a803990SChun-Jie Chen 89*4a803990SChun-Jie Chen - | 90*4a803990SChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 91*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 92*4a803990SChun-Jie Chen reg = <0x11e01000 0x1000>; 93*4a803990SChun-Jie Chen #clock-cells = <1>; 94*4a803990SChun-Jie Chen }; 95*4a803990SChun-Jie Chen 96*4a803990SChun-Jie Chen - | 97*4a803990SChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 98*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 99*4a803990SChun-Jie Chen reg = <0x11f02000 0x1000>; 100*4a803990SChun-Jie Chen #clock-cells = <1>; 101*4a803990SChun-Jie Chen }; 102*4a803990SChun-Jie Chen 103*4a803990SChun-Jie Chen - | 104*4a803990SChun-Jie Chen msdc_top: clock-controller@11f10000 { 105*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 106*4a803990SChun-Jie Chen reg = <0x11f10000 0x1000>; 107*4a803990SChun-Jie Chen #clock-cells = <1>; 108*4a803990SChun-Jie Chen }; 109*4a803990SChun-Jie Chen 110*4a803990SChun-Jie Chen - | 111*4a803990SChun-Jie Chen msdc: clock-controller@11f60000 { 112*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 113*4a803990SChun-Jie Chen reg = <0x11f60000 0x1000>; 114*4a803990SChun-Jie Chen #clock-cells = <1>; 115*4a803990SChun-Jie Chen }; 116*4a803990SChun-Jie Chen 117*4a803990SChun-Jie Chen - | 118*4a803990SChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 119*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 120*4a803990SChun-Jie Chen reg = <0x13fbf000 0x1000>; 121*4a803990SChun-Jie Chen #clock-cells = <1>; 122*4a803990SChun-Jie Chen }; 123*4a803990SChun-Jie Chen 124*4a803990SChun-Jie Chen - | 125*4a803990SChun-Jie Chen imgsys: clock-controller@15020000 { 126*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 127*4a803990SChun-Jie Chen reg = <0x15020000 0x1000>; 128*4a803990SChun-Jie Chen #clock-cells = <1>; 129*4a803990SChun-Jie Chen }; 130*4a803990SChun-Jie Chen 131*4a803990SChun-Jie Chen - | 132*4a803990SChun-Jie Chen imgsys2: clock-controller@15820000 { 133*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 134*4a803990SChun-Jie Chen reg = <0x15820000 0x1000>; 135*4a803990SChun-Jie Chen #clock-cells = <1>; 136*4a803990SChun-Jie Chen }; 137*4a803990SChun-Jie Chen 138*4a803990SChun-Jie Chen - | 139*4a803990SChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 140*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 141*4a803990SChun-Jie Chen reg = <0x1600f000 0x1000>; 142*4a803990SChun-Jie Chen #clock-cells = <1>; 143*4a803990SChun-Jie Chen }; 144*4a803990SChun-Jie Chen 145*4a803990SChun-Jie Chen - | 146*4a803990SChun-Jie Chen vdecsys: clock-controller@1602f000 { 147*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 148*4a803990SChun-Jie Chen reg = <0x1602f000 0x1000>; 149*4a803990SChun-Jie Chen #clock-cells = <1>; 150*4a803990SChun-Jie Chen }; 151*4a803990SChun-Jie Chen 152*4a803990SChun-Jie Chen - | 153*4a803990SChun-Jie Chen vencsys: clock-controller@17000000 { 154*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 155*4a803990SChun-Jie Chen reg = <0x17000000 0x1000>; 156*4a803990SChun-Jie Chen #clock-cells = <1>; 157*4a803990SChun-Jie Chen }; 158*4a803990SChun-Jie Chen 159*4a803990SChun-Jie Chen - | 160*4a803990SChun-Jie Chen camsys: clock-controller@1a000000 { 161*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 162*4a803990SChun-Jie Chen reg = <0x1a000000 0x1000>; 163*4a803990SChun-Jie Chen #clock-cells = <1>; 164*4a803990SChun-Jie Chen }; 165*4a803990SChun-Jie Chen 166*4a803990SChun-Jie Chen - | 167*4a803990SChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 168*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 169*4a803990SChun-Jie Chen reg = <0x1a04f000 0x1000>; 170*4a803990SChun-Jie Chen #clock-cells = <1>; 171*4a803990SChun-Jie Chen }; 172*4a803990SChun-Jie Chen 173*4a803990SChun-Jie Chen - | 174*4a803990SChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 175*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 176*4a803990SChun-Jie Chen reg = <0x1a06f000 0x1000>; 177*4a803990SChun-Jie Chen #clock-cells = <1>; 178*4a803990SChun-Jie Chen }; 179*4a803990SChun-Jie Chen 180*4a803990SChun-Jie Chen - | 181*4a803990SChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 182*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 183*4a803990SChun-Jie Chen reg = <0x1a08f000 0x1000>; 184*4a803990SChun-Jie Chen #clock-cells = <1>; 185*4a803990SChun-Jie Chen }; 186*4a803990SChun-Jie Chen 187*4a803990SChun-Jie Chen - | 188*4a803990SChun-Jie Chen ipesys: clock-controller@1b000000 { 189*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 190*4a803990SChun-Jie Chen reg = <0x1b000000 0x1000>; 191*4a803990SChun-Jie Chen #clock-cells = <1>; 192*4a803990SChun-Jie Chen }; 193*4a803990SChun-Jie Chen 194*4a803990SChun-Jie Chen - | 195*4a803990SChun-Jie Chen mdpsys: clock-controller@1f000000 { 196*4a803990SChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 197*4a803990SChun-Jie Chen reg = <0x1f000000 0x1000>; 198*4a803990SChun-Jie Chen #clock-cells = <1>; 199*4a803990SChun-Jie Chen }; 200