1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: MediaTek mmsys controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek mmsys system controller provides clock control, routing control,
14  and miscellaneous control in mmsys partition.
15
16properties:
17  $nodename:
18    pattern: "^syscon@[0-9a-f]+$"
19
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-mmsys
25              - mediatek,mt2712-mmsys
26              - mediatek,mt6765-mmsys
27              - mediatek,mt6779-mmsys
28              - mediatek,mt6795-mmsys
29              - mediatek,mt6797-mmsys
30              - mediatek,mt8167-mmsys
31              - mediatek,mt8173-mmsys
32              - mediatek,mt8183-mmsys
33              - mediatek,mt8186-mmsys
34              - mediatek,mt8188-vdosys0
35              - mediatek,mt8192-mmsys
36              - mediatek,mt8195-vdosys1
37              - mediatek,mt8365-mmsys
38          - const: syscon
39
40      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
41                     so mt8195 binding should be deprecated.
42        deprecated: true
43        items:
44          - const: mediatek,mt8195-mmsys
45          - const: syscon
46
47      - items:
48          - const: mediatek,mt7623-mmsys
49          - const: mediatek,mt2701-mmsys
50          - const: syscon
51
52      - items:
53          - const: mediatek,mt8195-vdosys0
54          - const: mediatek,mt8195-mmsys
55          - const: syscon
56
57  reg:
58    maxItems: 1
59
60  power-domains:
61    description:
62      A phandle and PM domain specifier as defined by bindings
63      of the power controller specified by phandle. See
64      Documentation/devicetree/bindings/power/power-domain.yaml for details.
65
66  mboxes:
67    description:
68      Using mailbox to communicate with GCE, it should have this
69      property and list of phandle, mailbox specifiers. See
70      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
71      for details.
72    $ref: /schemas/types.yaml#/definitions/phandle-array
73
74  mediatek,gce-client-reg:
75    description:
76      The register of client driver can be configured by gce with 4 arguments
77      defined in this property, such as phandle of gce, subsys id,
78      register offset and size.
79      Each subsys id is mapping to a base address of display function blocks
80      register which is defined in the gce header
81      include/dt-bindings/gce/<chip>-gce.h.
82    $ref: /schemas/types.yaml#/definitions/phandle-array
83    maxItems: 1
84
85  "#clock-cells":
86    const: 1
87
88  '#reset-cells':
89    const: 1
90
91required:
92  - compatible
93  - reg
94  - "#clock-cells"
95
96additionalProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/power/mt8173-power.h>
101    #include <dt-bindings/gce/mt8173-gce.h>
102
103    mmsys: syscon@14000000 {
104        compatible = "mediatek,mt8173-mmsys", "syscon";
105        reg = <0x14000000 0x1000>;
106        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
107        #clock-cells = <1>;
108        #reset-cells = <1>;
109        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
110                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
111        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
112    };
113