1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: MediaTek mmsys controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek mmsys system controller provides clock control, routing control,
14  and miscellaneous control in mmsys partition.
15
16properties:
17  $nodename:
18    pattern: "^syscon@[0-9a-f]+$"
19
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-mmsys
25              - mediatek,mt2712-mmsys
26              - mediatek,mt6765-mmsys
27              - mediatek,mt6779-mmsys
28              - mediatek,mt6795-mmsys
29              - mediatek,mt6797-mmsys
30              - mediatek,mt8167-mmsys
31              - mediatek,mt8173-mmsys
32              - mediatek,mt8183-mmsys
33              - mediatek,mt8186-mmsys
34              - mediatek,mt8188-vdosys0
35              - mediatek,mt8192-mmsys
36              - mediatek,mt8365-mmsys
37          - const: syscon
38
39      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
40                     so mt8195 binding should be deprecated.
41        deprecated: true
42        items:
43          - const: mediatek,mt8195-mmsys
44          - const: syscon
45
46      - items:
47          - const: mediatek,mt7623-mmsys
48          - const: mediatek,mt2701-mmsys
49          - const: syscon
50
51      - items:
52          - const: mediatek,mt8195-vdosys0
53          - const: mediatek,mt8195-mmsys
54          - const: syscon
55
56  reg:
57    maxItems: 1
58
59  power-domains:
60    description:
61      A phandle and PM domain specifier as defined by bindings
62      of the power controller specified by phandle. See
63      Documentation/devicetree/bindings/power/power-domain.yaml for details.
64
65  mboxes:
66    description:
67      Using mailbox to communicate with GCE, it should have this
68      property and list of phandle, mailbox specifiers. See
69      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
70      for details.
71    $ref: /schemas/types.yaml#/definitions/phandle-array
72
73  mediatek,gce-client-reg:
74    description:
75      The register of client driver can be configured by gce with 4 arguments
76      defined in this property, such as phandle of gce, subsys id,
77      register offset and size.
78      Each subsys id is mapping to a base address of display function blocks
79      register which is defined in the gce header
80      include/dt-bindings/gce/<chip>-gce.h.
81    $ref: /schemas/types.yaml#/definitions/phandle-array
82    maxItems: 1
83
84  "#clock-cells":
85    const: 1
86
87  '#reset-cells':
88    const: 1
89
90required:
91  - compatible
92  - reg
93  - "#clock-cells"
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/power/mt8173-power.h>
100    #include <dt-bindings/gce/mt8173-gce.h>
101
102    mmsys: syscon@14000000 {
103        compatible = "mediatek,mt8173-mmsys", "syscon";
104        reg = <0x14000000 0x1000>;
105        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
106        #clock-cells = <1>;
107        #reset-cells = <1>;
108        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
109                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
110        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
111    };
112