1eb522df4Sweiyi.lu@mediatek.comMediatek mcucfg controller
2eb522df4Sweiyi.lu@mediatek.com============================
3eb522df4Sweiyi.lu@mediatek.com
4eb522df4Sweiyi.lu@mediatek.comThe Mediatek mcucfg controller provides various clocks to the system.
5eb522df4Sweiyi.lu@mediatek.com
6eb522df4Sweiyi.lu@mediatek.comRequired Properties:
7eb522df4Sweiyi.lu@mediatek.com
8eb522df4Sweiyi.lu@mediatek.com- compatible: Should be one of:
9eb522df4Sweiyi.lu@mediatek.com	- "mediatek,mt2712-mcucfg", "syscon"
102f41cd9bSWeiyi Lu	- "mediatek,mt8183-mcucfg", "syscon"
11eb522df4Sweiyi.lu@mediatek.com- #clock-cells: Must be 1
12eb522df4Sweiyi.lu@mediatek.com
13eb522df4Sweiyi.lu@mediatek.comThe mcucfg controller uses the common clk binding from
14eb522df4Sweiyi.lu@mediatek.comDocumentation/devicetree/bindings/clock/clock-bindings.txt
15eb522df4Sweiyi.lu@mediatek.comThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
16eb522df4Sweiyi.lu@mediatek.com
17eb522df4Sweiyi.lu@mediatek.comExample:
18eb522df4Sweiyi.lu@mediatek.com
19eb522df4Sweiyi.lu@mediatek.commcucfg: syscon@10220000 {
20eb522df4Sweiyi.lu@mediatek.com	compatible = "mediatek,mt2712-mcucfg", "syscon";
21eb522df4Sweiyi.lu@mediatek.com	reg = <0 0x10220000 0 0x1000>;
22eb522df4Sweiyi.lu@mediatek.com	#clock-cells = <1>;
23eb522df4Sweiyi.lu@mediatek.com};
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