1eb522df4Sweiyi.lu@mediatek.comMediatek jpgdecsys controller
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3eb522df4Sweiyi.lu@mediatek.com
4eb522df4Sweiyi.lu@mediatek.comThe Mediatek jpgdecsys controller provides various clocks to the system.
5eb522df4Sweiyi.lu@mediatek.com
6eb522df4Sweiyi.lu@mediatek.comRequired Properties:
7eb522df4Sweiyi.lu@mediatek.com
8eb522df4Sweiyi.lu@mediatek.com- compatible: Should be:
9eb522df4Sweiyi.lu@mediatek.com	- "mediatek,mt2712-jpgdecsys", "syscon"
10eb522df4Sweiyi.lu@mediatek.com- #clock-cells: Must be 1
11eb522df4Sweiyi.lu@mediatek.com
12eb522df4Sweiyi.lu@mediatek.comThe jpgdecsys controller uses the common clk binding from
13eb522df4Sweiyi.lu@mediatek.comDocumentation/devicetree/bindings/clock/clock-bindings.txt
14eb522df4Sweiyi.lu@mediatek.comThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
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16eb522df4Sweiyi.lu@mediatek.comExample:
17eb522df4Sweiyi.lu@mediatek.com
18eb522df4Sweiyi.lu@mediatek.comjpgdecsys: syscon@19000000 {
19eb522df4Sweiyi.lu@mediatek.com	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
20eb522df4Sweiyi.lu@mediatek.com	reg = <0 0x19000000 0 0x1000>;
21eb522df4Sweiyi.lu@mediatek.com	#clock-cells = <1>;
22eb522df4Sweiyi.lu@mediatek.com};
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