14ae547ceSYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
24ae547ceSYassine Oudjana%YAML 1.2
34ae547ceSYassine Oudjana---
44ae547ceSYassine Oudjana$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
54ae547ceSYassine Oudjana$schema: "http://devicetree.org/meta-schemas/core.yaml#"
64ae547ceSYassine Oudjana
74ae547ceSYassine Oudjanatitle: MediaTek Infrastructure System Configuration Controller
84ae547ceSYassine Oudjana
94ae547ceSYassine Oudjanamaintainers:
104ae547ceSYassine Oudjana  - Matthias Brugger <matthias.bgg@gmail.com>
114ae547ceSYassine Oudjana
124ae547ceSYassine Oudjanadescription:
134ae547ceSYassine Oudjana  The Mediatek infracfg controller provides various clocks and reset outputs
144ae547ceSYassine Oudjana  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
154ae547ceSYassine Oudjana  and reset values in <dt-bindings/reset/mt*-reset.h> and
164ae547ceSYassine Oudjana  <dt-bindings/reset/mt*-resets.h>.
174ae547ceSYassine Oudjana
184ae547ceSYassine Oudjanaproperties:
194ae547ceSYassine Oudjana  compatible:
204ae547ceSYassine Oudjana    oneOf:
214ae547ceSYassine Oudjana      - items:
224ae547ceSYassine Oudjana          - enum:
234ae547ceSYassine Oudjana              - mediatek,mt2701-infracfg
244ae547ceSYassine Oudjana              - mediatek,mt2712-infracfg
254ae547ceSYassine Oudjana              - mediatek,mt6765-infracfg
26d5099c95SAngeloGioacchino Del Regno              - mediatek,mt6795-infracfg
274ae547ceSYassine Oudjana              - mediatek,mt6779-infracfg_ao
284ae547ceSYassine Oudjana              - mediatek,mt6797-infracfg
294ae547ceSYassine Oudjana              - mediatek,mt7622-infracfg
304ae547ceSYassine Oudjana              - mediatek,mt7629-infracfg
31*cc4d9e0cSDaniel Golle              - mediatek,mt7981-infracfg
324ae547ceSYassine Oudjana              - mediatek,mt7986-infracfg
334ae547ceSYassine Oudjana              - mediatek,mt8135-infracfg
344ae547ceSYassine Oudjana              - mediatek,mt8167-infracfg
354ae547ceSYassine Oudjana              - mediatek,mt8173-infracfg
364ae547ceSYassine Oudjana              - mediatek,mt8183-infracfg
374ae547ceSYassine Oudjana              - mediatek,mt8516-infracfg
384ae547ceSYassine Oudjana          - const: syscon
394ae547ceSYassine Oudjana      - items:
404ae547ceSYassine Oudjana          - const: mediatek,mt7623-infracfg
414ae547ceSYassine Oudjana          - const: mediatek,mt2701-infracfg
424ae547ceSYassine Oudjana          - const: syscon
434ae547ceSYassine Oudjana
444ae547ceSYassine Oudjana  reg:
454ae547ceSYassine Oudjana    maxItems: 1
464ae547ceSYassine Oudjana
474ae547ceSYassine Oudjana  '#clock-cells':
484ae547ceSYassine Oudjana    const: 1
494ae547ceSYassine Oudjana
504ae547ceSYassine Oudjana  '#reset-cells':
514ae547ceSYassine Oudjana    const: 1
524ae547ceSYassine Oudjana
534ae547ceSYassine Oudjanarequired:
544ae547ceSYassine Oudjana  - compatible
554ae547ceSYassine Oudjana  - reg
564ae547ceSYassine Oudjana  - '#clock-cells'
574ae547ceSYassine Oudjana
584ae547ceSYassine Oudjanaif:
594ae547ceSYassine Oudjana  properties:
604ae547ceSYassine Oudjana    compatible:
614ae547ceSYassine Oudjana      contains:
624ae547ceSYassine Oudjana        enum:
634ae547ceSYassine Oudjana          - mediatek,mt2701-infracfg
644ae547ceSYassine Oudjana          - mediatek,mt2712-infracfg
65d5099c95SAngeloGioacchino Del Regno          - mediatek,mt6795-infracfg
664ae547ceSYassine Oudjana          - mediatek,mt7622-infracfg
674ae547ceSYassine Oudjana          - mediatek,mt7986-infracfg
684ae547ceSYassine Oudjana          - mediatek,mt8135-infracfg
694ae547ceSYassine Oudjana          - mediatek,mt8173-infracfg
704ae547ceSYassine Oudjana          - mediatek,mt8183-infracfg
714ae547ceSYassine Oudjanathen:
724ae547ceSYassine Oudjana  required:
734ae547ceSYassine Oudjana    - '#reset-cells'
744ae547ceSYassine Oudjana
754ae547ceSYassine OudjanaadditionalProperties: false
764ae547ceSYassine Oudjana
774ae547ceSYassine Oudjanaexamples:
784ae547ceSYassine Oudjana  - |
794ae547ceSYassine Oudjana    infracfg: clock-controller@10001000 {
804ae547ceSYassine Oudjana        compatible = "mediatek,mt8173-infracfg", "syscon";
814ae547ceSYassine Oudjana        reg = <0x10001000 0x1000>;
824ae547ceSYassine Oudjana        #clock-cells = <1>;
834ae547ceSYassine Oudjana        #reset-cells = <1>;
844ae547ceSYassine Oudjana    };
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