1*4ae547ceSYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*4ae547ceSYassine Oudjana%YAML 1.2
3*4ae547ceSYassine Oudjana---
4*4ae547ceSYassine Oudjana$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
5*4ae547ceSYassine Oudjana$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6*4ae547ceSYassine Oudjana
7*4ae547ceSYassine Oudjanatitle: MediaTek Infrastructure System Configuration Controller
8*4ae547ceSYassine Oudjana
9*4ae547ceSYassine Oudjanamaintainers:
10*4ae547ceSYassine Oudjana  - Matthias Brugger <matthias.bgg@gmail.com>
11*4ae547ceSYassine Oudjana
12*4ae547ceSYassine Oudjanadescription:
13*4ae547ceSYassine Oudjana  The Mediatek infracfg controller provides various clocks and reset outputs
14*4ae547ceSYassine Oudjana  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
15*4ae547ceSYassine Oudjana  and reset values in <dt-bindings/reset/mt*-reset.h> and
16*4ae547ceSYassine Oudjana  <dt-bindings/reset/mt*-resets.h>.
17*4ae547ceSYassine Oudjana
18*4ae547ceSYassine Oudjanaproperties:
19*4ae547ceSYassine Oudjana  compatible:
20*4ae547ceSYassine Oudjana    oneOf:
21*4ae547ceSYassine Oudjana      - items:
22*4ae547ceSYassine Oudjana          - enum:
23*4ae547ceSYassine Oudjana              - mediatek,mt2701-infracfg
24*4ae547ceSYassine Oudjana              - mediatek,mt2712-infracfg
25*4ae547ceSYassine Oudjana              - mediatek,mt6765-infracfg
26*4ae547ceSYassine Oudjana              - mediatek,mt6779-infracfg_ao
27*4ae547ceSYassine Oudjana              - mediatek,mt6797-infracfg
28*4ae547ceSYassine Oudjana              - mediatek,mt7622-infracfg
29*4ae547ceSYassine Oudjana              - mediatek,mt7629-infracfg
30*4ae547ceSYassine Oudjana              - mediatek,mt7986-infracfg
31*4ae547ceSYassine Oudjana              - mediatek,mt8135-infracfg
32*4ae547ceSYassine Oudjana              - mediatek,mt8167-infracfg
33*4ae547ceSYassine Oudjana              - mediatek,mt8173-infracfg
34*4ae547ceSYassine Oudjana              - mediatek,mt8183-infracfg
35*4ae547ceSYassine Oudjana              - mediatek,mt8516-infracfg
36*4ae547ceSYassine Oudjana          - const: syscon
37*4ae547ceSYassine Oudjana      - items:
38*4ae547ceSYassine Oudjana          - const: mediatek,mt7623-infracfg
39*4ae547ceSYassine Oudjana          - const: mediatek,mt2701-infracfg
40*4ae547ceSYassine Oudjana          - const: syscon
41*4ae547ceSYassine Oudjana
42*4ae547ceSYassine Oudjana  reg:
43*4ae547ceSYassine Oudjana    maxItems: 1
44*4ae547ceSYassine Oudjana
45*4ae547ceSYassine Oudjana  '#clock-cells':
46*4ae547ceSYassine Oudjana    const: 1
47*4ae547ceSYassine Oudjana
48*4ae547ceSYassine Oudjana  '#reset-cells':
49*4ae547ceSYassine Oudjana    const: 1
50*4ae547ceSYassine Oudjana
51*4ae547ceSYassine Oudjanarequired:
52*4ae547ceSYassine Oudjana  - compatible
53*4ae547ceSYassine Oudjana  - reg
54*4ae547ceSYassine Oudjana  - '#clock-cells'
55*4ae547ceSYassine Oudjana
56*4ae547ceSYassine Oudjanaif:
57*4ae547ceSYassine Oudjana  properties:
58*4ae547ceSYassine Oudjana    compatible:
59*4ae547ceSYassine Oudjana      contains:
60*4ae547ceSYassine Oudjana        enum:
61*4ae547ceSYassine Oudjana          - mediatek,mt2701-infracfg
62*4ae547ceSYassine Oudjana          - mediatek,mt2712-infracfg
63*4ae547ceSYassine Oudjana          - mediatek,mt7622-infracfg
64*4ae547ceSYassine Oudjana          - mediatek,mt7986-infracfg
65*4ae547ceSYassine Oudjana          - mediatek,mt8135-infracfg
66*4ae547ceSYassine Oudjana          - mediatek,mt8173-infracfg
67*4ae547ceSYassine Oudjana          - mediatek,mt8183-infracfg
68*4ae547ceSYassine Oudjanathen:
69*4ae547ceSYassine Oudjana  required:
70*4ae547ceSYassine Oudjana    - '#reset-cells'
71*4ae547ceSYassine Oudjana
72*4ae547ceSYassine OudjanaadditionalProperties: false
73*4ae547ceSYassine Oudjana
74*4ae547ceSYassine Oudjanaexamples:
75*4ae547ceSYassine Oudjana  - |
76*4ae547ceSYassine Oudjana    infracfg: clock-controller@10001000 {
77*4ae547ceSYassine Oudjana        compatible = "mediatek,mt8173-infracfg", "syscon";
78*4ae547ceSYassine Oudjana        reg = <0x10001000 0x1000>;
79*4ae547ceSYassine Oudjana        #clock-cells = <1>;
80*4ae547ceSYassine Oudjana        #reset-cells = <1>;
81*4ae547ceSYassine Oudjana    };
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