156618489SJames LiaoMediatek imgsys controller 256618489SJames Liao============================ 356618489SJames Liao 456618489SJames LiaoThe Mediatek imgsys controller provides various clocks to the system. 556618489SJames Liao 656618489SJames LiaoRequired Properties: 756618489SJames Liao 86a588703SJames Liao- compatible: Should be one of: 96a588703SJames Liao - "mediatek,mt2701-imgsys", "syscon" 10eb522df4Sweiyi.lu@mediatek.com - "mediatek,mt2712-imgsys", "syscon" 11171f68a3Smtk01761 - "mediatek,mt6779-imgsys", "syscon" 122b51f514SKevin-CW Chen - "mediatek,mt6797-imgsys", "syscon" 13fd2a9f18SMatthias Brugger - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" 1456618489SJames Liao - "mediatek,mt8173-imgsys", "syscon" 152f41cd9bSWeiyi Lu - "mediatek,mt8183-imgsys", "syscon" 1656618489SJames Liao- #clock-cells: Must be 1 1756618489SJames Liao 1856618489SJames LiaoThe imgsys controller uses the common clk binding from 1956618489SJames LiaoDocumentation/devicetree/bindings/clock/clock-bindings.txt 2056618489SJames LiaoThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 2156618489SJames Liao 2256618489SJames LiaoExample: 2356618489SJames Liao 2456618489SJames Liaoimgsys: clock-controller@15000000 { 2556618489SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 2656618489SJames Liao reg = <0 0x15000000 0 0x1000>; 2756618489SJames Liao #clock-cells = <1>; 2856618489SJames Liao}; 29