16a588703SJames LiaoMediatek hifsys controller 26a588703SJames Liao============================ 36a588703SJames Liao 46a588703SJames LiaoThe Mediatek hifsys controller provides various clocks and reset 56a588703SJames Liaooutputs to the system. 66a588703SJames Liao 76a588703SJames LiaoRequired Properties: 86a588703SJames Liao 96a588703SJames Liao- compatible: Should be: 106a588703SJames Liao - "mediatek,mt2701-hifsys", "syscon" 11808ecf4aSSean Wang - "mediatek,mt7622-hifsys", "syscon" 12fd2a9f18SMatthias Brugger - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" 136a588703SJames Liao- #clock-cells: Must be 1 146a588703SJames Liao 156a588703SJames LiaoThe hifsys controller uses the common clk binding from 166a588703SJames LiaoDocumentation/devicetree/bindings/clock/clock-bindings.txt 176a588703SJames LiaoThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 186a588703SJames Liao 196a588703SJames LiaoExample: 206a588703SJames Liao 216a588703SJames Liaohifsys: clock-controller@1a000000 { 226a588703SJames Liao compatible = "mediatek,mt2701-hifsys", "syscon"; 236a588703SJames Liao reg = <0 0x1a000000 0 0x1000>; 246a588703SJames Liao #clock-cells = <1>; 256a588703SJames Liao #reset-cells = <1>; 266a588703SJames Liao}; 27