1*a505e52aSAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a505e52aSAnson Huang%YAML 1.2 3*a505e52aSAnson Huang--- 4*a505e52aSAnson Huang$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml# 5*a505e52aSAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a505e52aSAnson Huang 7*a505e52aSAnson Huangtitle: Freescale i.MX7ULP System Integration Module 8*a505e52aSAnson Huang 9*a505e52aSAnson Huangmaintainers: 10*a505e52aSAnson Huang - Anson Huang <anson.huang@nxp.com> 11*a505e52aSAnson Huang 12*a505e52aSAnson Huangdescription: | 13*a505e52aSAnson Huang The system integration module (SIM) provides system control and chip configuration 14*a505e52aSAnson Huang registers. In this module, chip revision information is located in JTAG ID register, 15*a505e52aSAnson Huang and a set of registers have been made available in DGO domain for SW use, with the 16*a505e52aSAnson Huang objective to maintain its value between system resets. 17*a505e52aSAnson Huang 18*a505e52aSAnson Huangproperties: 19*a505e52aSAnson Huang compatible: 20*a505e52aSAnson Huang items: 21*a505e52aSAnson Huang - const: fsl,imx7ulp-sim 22*a505e52aSAnson Huang - const: syscon 23*a505e52aSAnson Huang 24*a505e52aSAnson Huang reg: 25*a505e52aSAnson Huang maxItems: 1 26*a505e52aSAnson Huang 27*a505e52aSAnson Huangrequired: 28*a505e52aSAnson Huang - compatible 29*a505e52aSAnson Huang - reg 30*a505e52aSAnson Huang 31*a505e52aSAnson HuangadditionalProperties: false 32*a505e52aSAnson Huang 33*a505e52aSAnson Huangexamples: 34*a505e52aSAnson Huang - | 35*a505e52aSAnson Huang sim@410a3000 { 36*a505e52aSAnson Huang compatible = "fsl,imx7ulp-sim", "syscon"; 37*a505e52aSAnson Huang reg = <0x410a3000 0x1000>; 38*a505e52aSAnson Huang }; 39