1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a78ae
142      - arm,cortex-a510
143      - arm,cortex-a710
144      - arm,cortex-m0
145      - arm,cortex-m0+
146      - arm,cortex-m1
147      - arm,cortex-m3
148      - arm,cortex-m4
149      - arm,cortex-r4
150      - arm,cortex-r5
151      - arm,cortex-r7
152      - arm,cortex-x1
153      - arm,cortex-x2
154      - arm,neoverse-e1
155      - arm,neoverse-n1
156      - arm,neoverse-n2
157      - arm,neoverse-v1
158      - brcm,brahma-b15
159      - brcm,brahma-b53
160      - brcm,vulcan
161      - cavium,thunder
162      - cavium,thunder2
163      - faraday,fa526
164      - intel,sa110
165      - intel,sa1100
166      - marvell,feroceon
167      - marvell,mohawk
168      - marvell,pj4a
169      - marvell,pj4b
170      - marvell,sheeva-v5
171      - marvell,sheeva-v7
172      - nvidia,tegra132-denver
173      - nvidia,tegra186-denver
174      - nvidia,tegra194-carmel
175      - qcom,krait
176      - qcom,kryo
177      - qcom,kryo240
178      - qcom,kryo250
179      - qcom,kryo260
180      - qcom,kryo280
181      - qcom,kryo385
182      - qcom,kryo468
183      - qcom,kryo485
184      - qcom,kryo560
185      - qcom,kryo570
186      - qcom,kryo685
187      - qcom,kryo780
188      - qcom,scorpion
189
190  enable-method:
191    $ref: '/schemas/types.yaml#/definitions/string'
192    oneOf:
193      # On ARM v8 64-bit this property is required
194      - enum:
195          - psci
196          - spin-table
197      # On ARM 32-bit systems this property is optional
198      - enum:
199          - actions,s500-smp
200          - allwinner,sun6i-a31
201          - allwinner,sun8i-a23
202          - allwinner,sun9i-a80-smp
203          - allwinner,sun8i-a83t-smp
204          - amlogic,meson8-smp
205          - amlogic,meson8b-smp
206          - arm,realview-smp
207          - aspeed,ast2600-smp
208          - brcm,bcm11351-cpu-method
209          - brcm,bcm23550
210          - brcm,bcm2836-smp
211          - brcm,bcm63138
212          - brcm,bcm-nsp-smp
213          - brcm,brahma-b15
214          - marvell,armada-375-smp
215          - marvell,armada-380-smp
216          - marvell,armada-390-smp
217          - marvell,armada-xp-smp
218          - marvell,98dx3236-smp
219          - marvell,mmp3-smp
220          - mediatek,mt6589-smp
221          - mediatek,mt81xx-tz-smp
222          - qcom,gcc-msm8660
223          - qcom,kpss-acc-v1
224          - qcom,kpss-acc-v2
225          - qcom,msm8226-smp
226          - qcom,msm8909-smp
227          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
228          - qcom,msm8916-smp
229          - renesas,apmu
230          - renesas,r9a06g032-smp
231          - rockchip,rk3036-smp
232          - rockchip,rk3066-smp
233          - socionext,milbeaut-m10v-smp
234          - ste,dbx500-smp
235          - ti,am3352
236          - ti,am4372
237
238  cpu-release-addr:
239    oneOf:
240      - $ref: '/schemas/types.yaml#/definitions/uint32'
241      - $ref: '/schemas/types.yaml#/definitions/uint64'
242    description:
243      The DT specification defines this as 64-bit always, but some 32-bit Arm
244      systems have used a 32-bit value which must be supported.
245      Required for systems that have an "enable-method"
246        property value of "spin-table".
247
248  cpu-idle-states:
249    $ref: '/schemas/types.yaml#/definitions/phandle-array'
250    items:
251      maxItems: 1
252    description: |
253      List of phandles to idle state nodes supported
254      by this cpu (see ./idle-states.yaml).
255
256  capacity-dmips-mhz:
257    description:
258      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
259      DMIPS/MHz, relative to highest capacity-dmips-mhz
260      in the system.
261
262  cci-control-port: true
263
264  dynamic-power-coefficient:
265    $ref: '/schemas/types.yaml#/definitions/uint32'
266    description:
267      A u32 value that represents the running time dynamic
268      power coefficient in units of uW/MHz/V^2. The
269      coefficient can either be calculated from power
270      measurements or derived by analysis.
271
272      The dynamic power consumption of the CPU  is
273      proportional to the square of the Voltage (V) and
274      the clock frequency (f). The coefficient is used to
275      calculate the dynamic power as below -
276
277      Pdyn = dynamic-power-coefficient * V^2 * f
278
279      where voltage is in V, frequency is in MHz.
280
281  performance-domains:
282    maxItems: 1
283    description:
284      List of phandles and performance domain specifiers, as defined by
285      bindings of the performance domain provider. See also
286      dvfs/performance-domain.yaml.
287
288  power-domains:
289    description:
290      List of phandles and PM domain specifiers, as defined by bindings of the
291      PM domain provider (see also ../power_domain.txt).
292
293  power-domain-names:
294    description:
295      A list of power domain name strings sorted in the same order as the
296      power-domains property.
297
298      For PSCI based platforms, the name corresponding to the index of the PSCI
299      PM domain provider, must be "psci".
300
301  qcom,saw:
302    $ref: '/schemas/types.yaml#/definitions/phandle'
303    description: |
304      Specifies the SAW* node associated with this CPU.
305
306      Required for systems that have an "enable-method" property
307      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
308
309      * arm/msm/qcom,saw2.txt
310
311  qcom,acc:
312    $ref: '/schemas/types.yaml#/definitions/phandle'
313    description: |
314      Specifies the ACC* node associated with this CPU.
315
316      Required for systems that have an "enable-method" property
317      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
318      "qcom,msm8916-smp".
319
320      * arm/msm/qcom,kpss-acc.txt
321
322  rockchip,pmu:
323    $ref: '/schemas/types.yaml#/definitions/phandle'
324    description: |
325      Specifies the syscon node controlling the cpu core power domains.
326
327      Optional for systems that have an "enable-method"
328      property value of "rockchip,rk3066-smp"
329      While optional, it is the preferred way to get access to
330      the cpu-core power-domains.
331
332  secondary-boot-reg:
333    $ref: '/schemas/types.yaml#/definitions/uint32'
334    description: |
335      Required for systems that have an "enable-method" property value of
336      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
337
338      This includes the following SoCs: |
339      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
340      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
341
342      The secondary-boot-reg property is a u32 value that specifies the
343      physical address of the register used to request the ROM holding pen
344      code release a secondary CPU. The value written to the register is
345      formed by encoding the target CPU id into the low bits of the
346      physical start address it should jump to.
347
348if:
349  # If the enable-method property contains one of those values
350  properties:
351    enable-method:
352      contains:
353        enum:
354          - brcm,bcm11351-cpu-method
355          - brcm,bcm23550
356          - brcm,bcm-nsp-smp
357  # and if enable-method is present
358  required:
359    - enable-method
360
361then:
362  required:
363    - secondary-boot-reg
364
365required:
366  - device_type
367  - reg
368  - compatible
369
370dependencies:
371  rockchip,pmu: [enable-method]
372
373additionalProperties: true
374
375examples:
376  - |
377    cpus {
378      #size-cells = <0>;
379      #address-cells = <1>;
380
381      cpu@0 {
382        device_type = "cpu";
383        compatible = "arm,cortex-a15";
384        reg = <0x0>;
385      };
386
387      cpu@1 {
388        device_type = "cpu";
389        compatible = "arm,cortex-a15";
390        reg = <0x1>;
391      };
392
393      cpu@100 {
394        device_type = "cpu";
395        compatible = "arm,cortex-a7";
396        reg = <0x100>;
397      };
398
399      cpu@101 {
400        device_type = "cpu";
401        compatible = "arm,cortex-a7";
402        reg = <0x101>;
403      };
404    };
405
406  - |
407    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
408    cpus {
409      #size-cells = <0>;
410      #address-cells = <1>;
411
412      cpu@0 {
413        device_type = "cpu";
414        compatible = "arm,cortex-a8";
415        reg = <0x0>;
416      };
417    };
418
419  - |
420    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
421    cpus {
422      #size-cells = <0>;
423      #address-cells = <1>;
424
425      cpu@0 {
426        device_type = "cpu";
427        compatible = "arm,arm926ej-s";
428        reg = <0x0>;
429      };
430    };
431
432  - |
433    //  Example 4 (ARM Cortex-A57 64-bit system):
434    cpus {
435      #size-cells = <0>;
436      #address-cells = <2>;
437
438      cpu@0 {
439        device_type = "cpu";
440        compatible = "arm,cortex-a57";
441        reg = <0x0 0x0>;
442        enable-method = "spin-table";
443        cpu-release-addr = <0 0x20000000>;
444      };
445
446      cpu@1 {
447        device_type = "cpu";
448        compatible = "arm,cortex-a57";
449        reg = <0x0 0x1>;
450        enable-method = "spin-table";
451        cpu-release-addr = <0 0x20000000>;
452      };
453
454      cpu@100 {
455        device_type = "cpu";
456        compatible = "arm,cortex-a57";
457        reg = <0x0 0x100>;
458        enable-method = "spin-table";
459        cpu-release-addr = <0 0x20000000>;
460      };
461
462      cpu@101 {
463        device_type = "cpu";
464        compatible = "arm,cortex-a57";
465        reg = <0x0 0x101>;
466        enable-method = "spin-table";
467        cpu-release-addr = <0 0x20000000>;
468      };
469
470      cpu@10000 {
471        device_type = "cpu";
472        compatible = "arm,cortex-a57";
473        reg = <0x0 0x10000>;
474        enable-method = "spin-table";
475        cpu-release-addr = <0 0x20000000>;
476      };
477
478      cpu@10001 {
479        device_type = "cpu";
480        compatible = "arm,cortex-a57";
481        reg = <0x0 0x10001>;
482        enable-method = "spin-table";
483        cpu-release-addr = <0 0x20000000>;
484      };
485
486      cpu@10100 {
487        device_type = "cpu";
488        compatible = "arm,cortex-a57";
489        reg = <0x0 0x10100>;
490        enable-method = "spin-table";
491        cpu-release-addr = <0 0x20000000>;
492      };
493
494      cpu@10101 {
495        device_type = "cpu";
496        compatible = "arm,cortex-a57";
497        reg = <0x0 0x10101>;
498        enable-method = "spin-table";
499        cpu-release-addr = <0 0x20000000>;
500      };
501
502      cpu@100000000 {
503        device_type = "cpu";
504        compatible = "arm,cortex-a57";
505        reg = <0x1 0x0>;
506        enable-method = "spin-table";
507        cpu-release-addr = <0 0x20000000>;
508      };
509
510      cpu@100000001 {
511        device_type = "cpu";
512        compatible = "arm,cortex-a57";
513        reg = <0x1 0x1>;
514        enable-method = "spin-table";
515        cpu-release-addr = <0 0x20000000>;
516      };
517
518      cpu@100000100 {
519        device_type = "cpu";
520        compatible = "arm,cortex-a57";
521        reg = <0x1 0x100>;
522        enable-method = "spin-table";
523        cpu-release-addr = <0 0x20000000>;
524      };
525
526      cpu@100000101 {
527        device_type = "cpu";
528        compatible = "arm,cortex-a57";
529        reg = <0x1 0x101>;
530        enable-method = "spin-table";
531        cpu-release-addr = <0 0x20000000>;
532      };
533
534      cpu@100010000 {
535        device_type = "cpu";
536        compatible = "arm,cortex-a57";
537        reg = <0x1 0x10000>;
538        enable-method = "spin-table";
539        cpu-release-addr = <0 0x20000000>;
540      };
541
542      cpu@100010001 {
543        device_type = "cpu";
544        compatible = "arm,cortex-a57";
545        reg = <0x1 0x10001>;
546        enable-method = "spin-table";
547        cpu-release-addr = <0 0x20000000>;
548      };
549
550      cpu@100010100 {
551        device_type = "cpu";
552        compatible = "arm,cortex-a57";
553        reg = <0x1 0x10100>;
554        enable-method = "spin-table";
555        cpu-release-addr = <0 0x20000000>;
556      };
557
558      cpu@100010101 {
559        device_type = "cpu";
560        compatible = "arm,cortex-a57";
561        reg = <0x1 0x10101>;
562        enable-method = "spin-table";
563        cpu-release-addr = <0 0x20000000>;
564      };
565    };
566...
567