1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a53
127      - arm,cortex-a55
128      - arm,cortex-a57
129      - arm,cortex-a72
130      - arm,cortex-a73
131      - arm,cortex-m0
132      - arm,cortex-m0+
133      - arm,cortex-m1
134      - arm,cortex-m3
135      - arm,cortex-m4
136      - arm,cortex-r4
137      - arm,cortex-r5
138      - arm,cortex-r7
139      - brcm,brahma-b15
140      - brcm,brahma-b53
141      - brcm,vulcan
142      - cavium,thunder
143      - cavium,thunder2
144      - faraday,fa526
145      - intel,sa110
146      - intel,sa1100
147      - marvell,feroceon
148      - marvell,mohawk
149      - marvell,pj4a
150      - marvell,pj4b
151      - marvell,sheeva-v5
152      - marvell,sheeva-v7
153      - nvidia,tegra132-denver
154      - nvidia,tegra186-denver
155      - nvidia,tegra194-carmel
156      - qcom,krait
157      - qcom,kryo
158      - qcom,kryo385
159      - qcom,kryo485
160      - qcom,scorpion
161
162  enable-method:
163    allOf:
164      - $ref: '/schemas/types.yaml#/definitions/string'
165      - oneOf:
166          # On ARM v8 64-bit this property is required
167          - enum:
168              - psci
169              - spin-table
170          # On ARM 32-bit systems this property is optional
171          - enum:
172              - actions,s500-smp
173              - allwinner,sun6i-a31
174              - allwinner,sun8i-a23
175              - allwinner,sun9i-a80-smp
176              - allwinner,sun8i-a83t-smp
177              - amlogic,meson8-smp
178              - amlogic,meson8b-smp
179              - arm,realview-smp
180              - aspeed,ast2600-smp
181              - brcm,bcm11351-cpu-method
182              - brcm,bcm23550
183              - brcm,bcm2836-smp
184              - brcm,bcm63138
185              - brcm,bcm-nsp-smp
186              - brcm,brahma-b15
187              - marvell,armada-375-smp
188              - marvell,armada-380-smp
189              - marvell,armada-390-smp
190              - marvell,armada-xp-smp
191              - marvell,98dx3236-smp
192              - marvell,mmp3-smp
193              - mediatek,mt6589-smp
194              - mediatek,mt81xx-tz-smp
195              - qcom,gcc-msm8660
196              - qcom,kpss-acc-v1
197              - qcom,kpss-acc-v2
198              - renesas,apmu
199              - renesas,r9a06g032-smp
200              - rockchip,rk3036-smp
201              - rockchip,rk3066-smp
202              - socionext,milbeaut-m10v-smp
203              - ste,dbx500-smp
204              - ti,am3352
205              - ti,am4372
206
207  cpu-release-addr:
208    $ref: '/schemas/types.yaml#/definitions/uint64'
209
210    description:
211      Required for systems that have an "enable-method"
212        property value of "spin-table".
213      On ARM v8 64-bit systems must be a two cell
214        property identifying a 64-bit zero-initialised
215        memory location.
216
217  cpu-idle-states:
218    $ref: '/schemas/types.yaml#/definitions/phandle-array'
219    description: |
220      List of phandles to idle state nodes supported
221      by this cpu (see ./idle-states.txt).
222
223  capacity-dmips-mhz:
224    $ref: '/schemas/types.yaml#/definitions/uint32'
225    description:
226      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
227      DMIPS/MHz, relative to highest capacity-dmips-mhz
228      in the system.
229
230  dynamic-power-coefficient:
231    $ref: '/schemas/types.yaml#/definitions/uint32'
232    description:
233      A u32 value that represents the running time dynamic
234      power coefficient in units of uW/MHz/V^2. The
235      coefficient can either be calculated from power
236      measurements or derived by analysis.
237
238      The dynamic power consumption of the CPU  is
239      proportional to the square of the Voltage (V) and
240      the clock frequency (f). The coefficient is used to
241      calculate the dynamic power as below -
242
243      Pdyn = dynamic-power-coefficient * V^2 * f
244
245      where voltage is in V, frequency is in MHz.
246
247  power-domains:
248    $ref: '/schemas/types.yaml#/definitions/phandle-array'
249    description:
250      List of phandles and PM domain specifiers, as defined by bindings of the
251      PM domain provider (see also ../power_domain.txt).
252
253  power-domain-names:
254    $ref: '/schemas/types.yaml#/definitions/string-array'
255    description:
256      A list of power domain name strings sorted in the same order as the
257      power-domains property.
258
259      For PSCI based platforms, the name corresponding to the index of the PSCI
260      PM domain provider, must be "psci".
261
262  qcom,saw:
263    $ref: '/schemas/types.yaml#/definitions/phandle'
264    description: |
265      Specifies the SAW* node associated with this CPU.
266
267      Required for systems that have an "enable-method" property
268      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
269
270      * arm/msm/qcom,saw2.txt
271
272  qcom,acc:
273    $ref: '/schemas/types.yaml#/definitions/phandle'
274    description: |
275      Specifies the ACC* node associated with this CPU.
276
277      Required for systems that have an "enable-method" property
278      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
279
280      * arm/msm/qcom,kpss-acc.txt
281
282  rockchip,pmu:
283    $ref: '/schemas/types.yaml#/definitions/phandle'
284    description: |
285      Specifies the syscon node controlling the cpu core power domains.
286
287      Optional for systems that have an "enable-method"
288      property value of "rockchip,rk3066-smp"
289      While optional, it is the preferred way to get access to
290      the cpu-core power-domains.
291
292required:
293  - device_type
294  - reg
295  - compatible
296
297dependencies:
298  rockchip,pmu: [enable-method]
299
300examples:
301  - |
302    cpus {
303      #size-cells = <0>;
304      #address-cells = <1>;
305
306      cpu@0 {
307        device_type = "cpu";
308        compatible = "arm,cortex-a15";
309        reg = <0x0>;
310      };
311
312      cpu@1 {
313        device_type = "cpu";
314        compatible = "arm,cortex-a15";
315        reg = <0x1>;
316      };
317
318      cpu@100 {
319        device_type = "cpu";
320        compatible = "arm,cortex-a7";
321        reg = <0x100>;
322      };
323
324      cpu@101 {
325        device_type = "cpu";
326        compatible = "arm,cortex-a7";
327        reg = <0x101>;
328      };
329    };
330
331  - |
332    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
333    cpus {
334      #size-cells = <0>;
335      #address-cells = <1>;
336
337      cpu@0 {
338        device_type = "cpu";
339        compatible = "arm,cortex-a8";
340        reg = <0x0>;
341      };
342    };
343
344  - |
345    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
346    cpus {
347      #size-cells = <0>;
348      #address-cells = <1>;
349
350      cpu@0 {
351        device_type = "cpu";
352        compatible = "arm,arm926ej-s";
353        reg = <0x0>;
354      };
355    };
356
357  - |
358    //  Example 4 (ARM Cortex-A57 64-bit system):
359    cpus {
360      #size-cells = <0>;
361      #address-cells = <2>;
362
363      cpu@0 {
364        device_type = "cpu";
365        compatible = "arm,cortex-a57";
366        reg = <0x0 0x0>;
367        enable-method = "spin-table";
368        cpu-release-addr = <0 0x20000000>;
369      };
370
371      cpu@1 {
372        device_type = "cpu";
373        compatible = "arm,cortex-a57";
374        reg = <0x0 0x1>;
375        enable-method = "spin-table";
376        cpu-release-addr = <0 0x20000000>;
377      };
378
379      cpu@100 {
380        device_type = "cpu";
381        compatible = "arm,cortex-a57";
382        reg = <0x0 0x100>;
383        enable-method = "spin-table";
384        cpu-release-addr = <0 0x20000000>;
385      };
386
387      cpu@101 {
388        device_type = "cpu";
389        compatible = "arm,cortex-a57";
390        reg = <0x0 0x101>;
391        enable-method = "spin-table";
392        cpu-release-addr = <0 0x20000000>;
393      };
394
395      cpu@10000 {
396        device_type = "cpu";
397        compatible = "arm,cortex-a57";
398        reg = <0x0 0x10000>;
399        enable-method = "spin-table";
400        cpu-release-addr = <0 0x20000000>;
401      };
402
403      cpu@10001 {
404        device_type = "cpu";
405        compatible = "arm,cortex-a57";
406        reg = <0x0 0x10001>;
407        enable-method = "spin-table";
408        cpu-release-addr = <0 0x20000000>;
409      };
410
411      cpu@10100 {
412        device_type = "cpu";
413        compatible = "arm,cortex-a57";
414        reg = <0x0 0x10100>;
415        enable-method = "spin-table";
416        cpu-release-addr = <0 0x20000000>;
417      };
418
419      cpu@10101 {
420        device_type = "cpu";
421        compatible = "arm,cortex-a57";
422        reg = <0x0 0x10101>;
423        enable-method = "spin-table";
424        cpu-release-addr = <0 0x20000000>;
425      };
426
427      cpu@100000000 {
428        device_type = "cpu";
429        compatible = "arm,cortex-a57";
430        reg = <0x1 0x0>;
431        enable-method = "spin-table";
432        cpu-release-addr = <0 0x20000000>;
433      };
434
435      cpu@100000001 {
436        device_type = "cpu";
437        compatible = "arm,cortex-a57";
438        reg = <0x1 0x1>;
439        enable-method = "spin-table";
440        cpu-release-addr = <0 0x20000000>;
441      };
442
443      cpu@100000100 {
444        device_type = "cpu";
445        compatible = "arm,cortex-a57";
446        reg = <0x1 0x100>;
447        enable-method = "spin-table";
448        cpu-release-addr = <0 0x20000000>;
449      };
450
451      cpu@100000101 {
452        device_type = "cpu";
453        compatible = "arm,cortex-a57";
454        reg = <0x1 0x101>;
455        enable-method = "spin-table";
456        cpu-release-addr = <0 0x20000000>;
457      };
458
459      cpu@100010000 {
460        device_type = "cpu";
461        compatible = "arm,cortex-a57";
462        reg = <0x1 0x10000>;
463        enable-method = "spin-table";
464        cpu-release-addr = <0 0x20000000>;
465      };
466
467      cpu@100010001 {
468        device_type = "cpu";
469        compatible = "arm,cortex-a57";
470        reg = <0x1 0x10001>;
471        enable-method = "spin-table";
472        cpu-release-addr = <0 0x20000000>;
473      };
474
475      cpu@100010100 {
476        device_type = "cpu";
477        compatible = "arm,cortex-a57";
478        reg = <0x1 0x10100>;
479        enable-method = "spin-table";
480        cpu-release-addr = <0 0x20000000>;
481      };
482
483      cpu@100010101 {
484        device_type = "cpu";
485        compatible = "arm,cortex-a57";
486        reg = <0x1 0x10101>;
487        enable-method = "spin-table";
488        cpu-release-addr = <0 0x20000000>;
489      };
490    };
491...
492