1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a510
142      - arm,cortex-a710
143      - arm,cortex-m0
144      - arm,cortex-m0+
145      - arm,cortex-m1
146      - arm,cortex-m3
147      - arm,cortex-m4
148      - arm,cortex-r4
149      - arm,cortex-r5
150      - arm,cortex-r7
151      - arm,cortex-x1
152      - arm,cortex-x2
153      - arm,neoverse-e1
154      - arm,neoverse-n1
155      - arm,neoverse-n2
156      - arm,neoverse-v1
157      - brcm,brahma-b15
158      - brcm,brahma-b53
159      - brcm,vulcan
160      - cavium,thunder
161      - cavium,thunder2
162      - faraday,fa526
163      - intel,sa110
164      - intel,sa1100
165      - marvell,feroceon
166      - marvell,mohawk
167      - marvell,pj4a
168      - marvell,pj4b
169      - marvell,sheeva-v5
170      - marvell,sheeva-v7
171      - nvidia,tegra132-denver
172      - nvidia,tegra186-denver
173      - nvidia,tegra194-carmel
174      - qcom,krait
175      - qcom,kryo
176      - qcom,kryo260
177      - qcom,kryo280
178      - qcom,kryo385
179      - qcom,kryo468
180      - qcom,kryo485
181      - qcom,kryo560
182      - qcom,kryo570
183      - qcom,kryo685
184      - qcom,kryo780
185      - qcom,scorpion
186
187  enable-method:
188    $ref: '/schemas/types.yaml#/definitions/string'
189    oneOf:
190      # On ARM v8 64-bit this property is required
191      - enum:
192          - psci
193          - spin-table
194      # On ARM 32-bit systems this property is optional
195      - enum:
196          - actions,s500-smp
197          - allwinner,sun6i-a31
198          - allwinner,sun8i-a23
199          - allwinner,sun9i-a80-smp
200          - allwinner,sun8i-a83t-smp
201          - amlogic,meson8-smp
202          - amlogic,meson8b-smp
203          - arm,realview-smp
204          - aspeed,ast2600-smp
205          - brcm,bcm11351-cpu-method
206          - brcm,bcm23550
207          - brcm,bcm2836-smp
208          - brcm,bcm63138
209          - brcm,bcm-nsp-smp
210          - brcm,brahma-b15
211          - marvell,armada-375-smp
212          - marvell,armada-380-smp
213          - marvell,armada-390-smp
214          - marvell,armada-xp-smp
215          - marvell,98dx3236-smp
216          - marvell,mmp3-smp
217          - mediatek,mt6589-smp
218          - mediatek,mt81xx-tz-smp
219          - qcom,gcc-msm8660
220          - qcom,kpss-acc-v1
221          - qcom,kpss-acc-v2
222          - qcom,msm8226-smp
223          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
224          - qcom,msm8916-smp
225          - renesas,apmu
226          - renesas,r9a06g032-smp
227          - rockchip,rk3036-smp
228          - rockchip,rk3066-smp
229          - socionext,milbeaut-m10v-smp
230          - ste,dbx500-smp
231          - ti,am3352
232          - ti,am4372
233
234  cpu-release-addr:
235    oneOf:
236      - $ref: '/schemas/types.yaml#/definitions/uint32'
237      - $ref: '/schemas/types.yaml#/definitions/uint64'
238    description:
239      The DT specification defines this as 64-bit always, but some 32-bit Arm
240      systems have used a 32-bit value which must be supported.
241      Required for systems that have an "enable-method"
242        property value of "spin-table".
243
244  cpu-idle-states:
245    $ref: '/schemas/types.yaml#/definitions/phandle-array'
246    items:
247      maxItems: 1
248    description: |
249      List of phandles to idle state nodes supported
250      by this cpu (see ./idle-states.yaml).
251
252  capacity-dmips-mhz:
253    description:
254      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
255      DMIPS/MHz, relative to highest capacity-dmips-mhz
256      in the system.
257
258  cci-control-port: true
259
260  dynamic-power-coefficient:
261    $ref: '/schemas/types.yaml#/definitions/uint32'
262    description:
263      A u32 value that represents the running time dynamic
264      power coefficient in units of uW/MHz/V^2. The
265      coefficient can either be calculated from power
266      measurements or derived by analysis.
267
268      The dynamic power consumption of the CPU  is
269      proportional to the square of the Voltage (V) and
270      the clock frequency (f). The coefficient is used to
271      calculate the dynamic power as below -
272
273      Pdyn = dynamic-power-coefficient * V^2 * f
274
275      where voltage is in V, frequency is in MHz.
276
277  performance-domains:
278    maxItems: 1
279    description:
280      List of phandles and performance domain specifiers, as defined by
281      bindings of the performance domain provider. See also
282      dvfs/performance-domain.yaml.
283
284  power-domains:
285    description:
286      List of phandles and PM domain specifiers, as defined by bindings of the
287      PM domain provider (see also ../power_domain.txt).
288
289  power-domain-names:
290    description:
291      A list of power domain name strings sorted in the same order as the
292      power-domains property.
293
294      For PSCI based platforms, the name corresponding to the index of the PSCI
295      PM domain provider, must be "psci".
296
297  qcom,saw:
298    $ref: '/schemas/types.yaml#/definitions/phandle'
299    description: |
300      Specifies the SAW* node associated with this CPU.
301
302      Required for systems that have an "enable-method" property
303      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
304
305      * arm/msm/qcom,saw2.txt
306
307  qcom,acc:
308    $ref: '/schemas/types.yaml#/definitions/phandle'
309    description: |
310      Specifies the ACC* node associated with this CPU.
311
312      Required for systems that have an "enable-method" property
313      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
314      "qcom,msm8916-smp".
315
316      * arm/msm/qcom,kpss-acc.txt
317
318  rockchip,pmu:
319    $ref: '/schemas/types.yaml#/definitions/phandle'
320    description: |
321      Specifies the syscon node controlling the cpu core power domains.
322
323      Optional for systems that have an "enable-method"
324      property value of "rockchip,rk3066-smp"
325      While optional, it is the preferred way to get access to
326      the cpu-core power-domains.
327
328  secondary-boot-reg:
329    $ref: '/schemas/types.yaml#/definitions/uint32'
330    description: |
331      Required for systems that have an "enable-method" property value of
332      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
333
334      This includes the following SoCs: |
335      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
336      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
337
338      The secondary-boot-reg property is a u32 value that specifies the
339      physical address of the register used to request the ROM holding pen
340      code release a secondary CPU. The value written to the register is
341      formed by encoding the target CPU id into the low bits of the
342      physical start address it should jump to.
343
344if:
345  # If the enable-method property contains one of those values
346  properties:
347    enable-method:
348      contains:
349        enum:
350          - brcm,bcm11351-cpu-method
351          - brcm,bcm23550
352          - brcm,bcm-nsp-smp
353  # and if enable-method is present
354  required:
355    - enable-method
356
357then:
358  required:
359    - secondary-boot-reg
360
361required:
362  - device_type
363  - reg
364  - compatible
365
366dependencies:
367  rockchip,pmu: [enable-method]
368
369additionalProperties: true
370
371examples:
372  - |
373    cpus {
374      #size-cells = <0>;
375      #address-cells = <1>;
376
377      cpu@0 {
378        device_type = "cpu";
379        compatible = "arm,cortex-a15";
380        reg = <0x0>;
381      };
382
383      cpu@1 {
384        device_type = "cpu";
385        compatible = "arm,cortex-a15";
386        reg = <0x1>;
387      };
388
389      cpu@100 {
390        device_type = "cpu";
391        compatible = "arm,cortex-a7";
392        reg = <0x100>;
393      };
394
395      cpu@101 {
396        device_type = "cpu";
397        compatible = "arm,cortex-a7";
398        reg = <0x101>;
399      };
400    };
401
402  - |
403    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
404    cpus {
405      #size-cells = <0>;
406      #address-cells = <1>;
407
408      cpu@0 {
409        device_type = "cpu";
410        compatible = "arm,cortex-a8";
411        reg = <0x0>;
412      };
413    };
414
415  - |
416    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
417    cpus {
418      #size-cells = <0>;
419      #address-cells = <1>;
420
421      cpu@0 {
422        device_type = "cpu";
423        compatible = "arm,arm926ej-s";
424        reg = <0x0>;
425      };
426    };
427
428  - |
429    //  Example 4 (ARM Cortex-A57 64-bit system):
430    cpus {
431      #size-cells = <0>;
432      #address-cells = <2>;
433
434      cpu@0 {
435        device_type = "cpu";
436        compatible = "arm,cortex-a57";
437        reg = <0x0 0x0>;
438        enable-method = "spin-table";
439        cpu-release-addr = <0 0x20000000>;
440      };
441
442      cpu@1 {
443        device_type = "cpu";
444        compatible = "arm,cortex-a57";
445        reg = <0x0 0x1>;
446        enable-method = "spin-table";
447        cpu-release-addr = <0 0x20000000>;
448      };
449
450      cpu@100 {
451        device_type = "cpu";
452        compatible = "arm,cortex-a57";
453        reg = <0x0 0x100>;
454        enable-method = "spin-table";
455        cpu-release-addr = <0 0x20000000>;
456      };
457
458      cpu@101 {
459        device_type = "cpu";
460        compatible = "arm,cortex-a57";
461        reg = <0x0 0x101>;
462        enable-method = "spin-table";
463        cpu-release-addr = <0 0x20000000>;
464      };
465
466      cpu@10000 {
467        device_type = "cpu";
468        compatible = "arm,cortex-a57";
469        reg = <0x0 0x10000>;
470        enable-method = "spin-table";
471        cpu-release-addr = <0 0x20000000>;
472      };
473
474      cpu@10001 {
475        device_type = "cpu";
476        compatible = "arm,cortex-a57";
477        reg = <0x0 0x10001>;
478        enable-method = "spin-table";
479        cpu-release-addr = <0 0x20000000>;
480      };
481
482      cpu@10100 {
483        device_type = "cpu";
484        compatible = "arm,cortex-a57";
485        reg = <0x0 0x10100>;
486        enable-method = "spin-table";
487        cpu-release-addr = <0 0x20000000>;
488      };
489
490      cpu@10101 {
491        device_type = "cpu";
492        compatible = "arm,cortex-a57";
493        reg = <0x0 0x10101>;
494        enable-method = "spin-table";
495        cpu-release-addr = <0 0x20000000>;
496      };
497
498      cpu@100000000 {
499        device_type = "cpu";
500        compatible = "arm,cortex-a57";
501        reg = <0x1 0x0>;
502        enable-method = "spin-table";
503        cpu-release-addr = <0 0x20000000>;
504      };
505
506      cpu@100000001 {
507        device_type = "cpu";
508        compatible = "arm,cortex-a57";
509        reg = <0x1 0x1>;
510        enable-method = "spin-table";
511        cpu-release-addr = <0 0x20000000>;
512      };
513
514      cpu@100000100 {
515        device_type = "cpu";
516        compatible = "arm,cortex-a57";
517        reg = <0x1 0x100>;
518        enable-method = "spin-table";
519        cpu-release-addr = <0 0x20000000>;
520      };
521
522      cpu@100000101 {
523        device_type = "cpu";
524        compatible = "arm,cortex-a57";
525        reg = <0x1 0x101>;
526        enable-method = "spin-table";
527        cpu-release-addr = <0 0x20000000>;
528      };
529
530      cpu@100010000 {
531        device_type = "cpu";
532        compatible = "arm,cortex-a57";
533        reg = <0x1 0x10000>;
534        enable-method = "spin-table";
535        cpu-release-addr = <0 0x20000000>;
536      };
537
538      cpu@100010001 {
539        device_type = "cpu";
540        compatible = "arm,cortex-a57";
541        reg = <0x1 0x10001>;
542        enable-method = "spin-table";
543        cpu-release-addr = <0 0x20000000>;
544      };
545
546      cpu@100010100 {
547        device_type = "cpu";
548        compatible = "arm,cortex-a57";
549        reg = <0x1 0x10100>;
550        enable-method = "spin-table";
551        cpu-release-addr = <0 0x20000000>;
552      };
553
554      cpu@100010101 {
555        device_type = "cpu";
556        compatible = "arm,cortex-a57";
557        reg = <0x1 0x10101>;
558        enable-method = "spin-table";
559        cpu-release-addr = <0 0x20000000>;
560      };
561    };
562...
563