1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-m0
141      - arm,cortex-m0+
142      - arm,cortex-m1
143      - arm,cortex-m3
144      - arm,cortex-m4
145      - arm,cortex-r4
146      - arm,cortex-r5
147      - arm,cortex-r7
148      - arm,neoverse-e1
149      - arm,neoverse-n1
150      - brcm,brahma-b15
151      - brcm,brahma-b53
152      - brcm,vulcan
153      - cavium,thunder
154      - cavium,thunder2
155      - faraday,fa526
156      - intel,sa110
157      - intel,sa1100
158      - marvell,feroceon
159      - marvell,mohawk
160      - marvell,pj4a
161      - marvell,pj4b
162      - marvell,sheeva-v5
163      - marvell,sheeva-v7
164      - nvidia,tegra132-denver
165      - nvidia,tegra186-denver
166      - nvidia,tegra194-carmel
167      - qcom,krait
168      - qcom,kryo
169      - qcom,kryo260
170      - qcom,kryo280
171      - qcom,kryo385
172      - qcom,kryo468
173      - qcom,kryo485
174      - qcom,kryo685
175      - qcom,scorpion
176
177  enable-method:
178    $ref: '/schemas/types.yaml#/definitions/string'
179    oneOf:
180      # On ARM v8 64-bit this property is required
181      - enum:
182          - psci
183          - spin-table
184      # On ARM 32-bit systems this property is optional
185      - enum:
186          - actions,s500-smp
187          - allwinner,sun6i-a31
188          - allwinner,sun8i-a23
189          - allwinner,sun9i-a80-smp
190          - allwinner,sun8i-a83t-smp
191          - amlogic,meson8-smp
192          - amlogic,meson8b-smp
193          - arm,realview-smp
194          - aspeed,ast2600-smp
195          - brcm,bcm11351-cpu-method
196          - brcm,bcm23550
197          - brcm,bcm2836-smp
198          - brcm,bcm63138
199          - brcm,bcm-nsp-smp
200          - brcm,brahma-b15
201          - marvell,armada-375-smp
202          - marvell,armada-380-smp
203          - marvell,armada-390-smp
204          - marvell,armada-xp-smp
205          - marvell,98dx3236-smp
206          - marvell,mmp3-smp
207          - mediatek,mt6589-smp
208          - mediatek,mt81xx-tz-smp
209          - qcom,gcc-msm8660
210          - qcom,kpss-acc-v1
211          - qcom,kpss-acc-v2
212          - renesas,apmu
213          - renesas,r9a06g032-smp
214          - rockchip,rk3036-smp
215          - rockchip,rk3066-smp
216          - socionext,milbeaut-m10v-smp
217          - ste,dbx500-smp
218          - ti,am3352
219          - ti,am4372
220
221  cpu-release-addr:
222    $ref: '/schemas/types.yaml#/definitions/uint64'
223
224    description:
225      Required for systems that have an "enable-method"
226        property value of "spin-table".
227      On ARM v8 64-bit systems must be a two cell
228        property identifying a 64-bit zero-initialised
229        memory location.
230
231  cpu-idle-states:
232    $ref: '/schemas/types.yaml#/definitions/phandle-array'
233    description: |
234      List of phandles to idle state nodes supported
235      by this cpu (see ./idle-states.yaml).
236
237  capacity-dmips-mhz:
238    description:
239      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
240      DMIPS/MHz, relative to highest capacity-dmips-mhz
241      in the system.
242
243  cci-control-port: true
244
245  dynamic-power-coefficient:
246    $ref: '/schemas/types.yaml#/definitions/uint32'
247    description:
248      A u32 value that represents the running time dynamic
249      power coefficient in units of uW/MHz/V^2. The
250      coefficient can either be calculated from power
251      measurements or derived by analysis.
252
253      The dynamic power consumption of the CPU  is
254      proportional to the square of the Voltage (V) and
255      the clock frequency (f). The coefficient is used to
256      calculate the dynamic power as below -
257
258      Pdyn = dynamic-power-coefficient * V^2 * f
259
260      where voltage is in V, frequency is in MHz.
261
262  performance-domains:
263    maxItems: 1
264    description:
265      List of phandles and performance domain specifiers, as defined by
266      bindings of the performance domain provider. See also
267      dvfs/performance-domain.yaml.
268
269  power-domains:
270    description:
271      List of phandles and PM domain specifiers, as defined by bindings of the
272      PM domain provider (see also ../power_domain.txt).
273
274  power-domain-names:
275    description:
276      A list of power domain name strings sorted in the same order as the
277      power-domains property.
278
279      For PSCI based platforms, the name corresponding to the index of the PSCI
280      PM domain provider, must be "psci".
281
282  qcom,saw:
283    $ref: '/schemas/types.yaml#/definitions/phandle'
284    description: |
285      Specifies the SAW* node associated with this CPU.
286
287      Required for systems that have an "enable-method" property
288      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
289
290      * arm/msm/qcom,saw2.txt
291
292  qcom,acc:
293    $ref: '/schemas/types.yaml#/definitions/phandle'
294    description: |
295      Specifies the ACC* node associated with this CPU.
296
297      Required for systems that have an "enable-method" property
298      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
299
300      * arm/msm/qcom,kpss-acc.txt
301
302  rockchip,pmu:
303    $ref: '/schemas/types.yaml#/definitions/phandle'
304    description: |
305      Specifies the syscon node controlling the cpu core power domains.
306
307      Optional for systems that have an "enable-method"
308      property value of "rockchip,rk3066-smp"
309      While optional, it is the preferred way to get access to
310      the cpu-core power-domains.
311
312  secondary-boot-reg:
313    $ref: '/schemas/types.yaml#/definitions/uint32'
314    description: |
315      Required for systems that have an "enable-method" property value of
316      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
317
318      This includes the following SoCs: |
319      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
320      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
321
322      The secondary-boot-reg property is a u32 value that specifies the
323      physical address of the register used to request the ROM holding pen
324      code release a secondary CPU. The value written to the register is
325      formed by encoding the target CPU id into the low bits of the
326      physical start address it should jump to.
327
328if:
329  # If the enable-method property contains one of those values
330  properties:
331    enable-method:
332      contains:
333        enum:
334          - brcm,bcm11351-cpu-method
335          - brcm,bcm23550
336          - brcm,bcm-nsp-smp
337  # and if enable-method is present
338  required:
339    - enable-method
340
341then:
342  required:
343    - secondary-boot-reg
344
345required:
346  - device_type
347  - reg
348  - compatible
349
350dependencies:
351  rockchip,pmu: [enable-method]
352
353additionalProperties: true
354
355examples:
356  - |
357    cpus {
358      #size-cells = <0>;
359      #address-cells = <1>;
360
361      cpu@0 {
362        device_type = "cpu";
363        compatible = "arm,cortex-a15";
364        reg = <0x0>;
365      };
366
367      cpu@1 {
368        device_type = "cpu";
369        compatible = "arm,cortex-a15";
370        reg = <0x1>;
371      };
372
373      cpu@100 {
374        device_type = "cpu";
375        compatible = "arm,cortex-a7";
376        reg = <0x100>;
377      };
378
379      cpu@101 {
380        device_type = "cpu";
381        compatible = "arm,cortex-a7";
382        reg = <0x101>;
383      };
384    };
385
386  - |
387    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
388    cpus {
389      #size-cells = <0>;
390      #address-cells = <1>;
391
392      cpu@0 {
393        device_type = "cpu";
394        compatible = "arm,cortex-a8";
395        reg = <0x0>;
396      };
397    };
398
399  - |
400    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
401    cpus {
402      #size-cells = <0>;
403      #address-cells = <1>;
404
405      cpu@0 {
406        device_type = "cpu";
407        compatible = "arm,arm926ej-s";
408        reg = <0x0>;
409      };
410    };
411
412  - |
413    //  Example 4 (ARM Cortex-A57 64-bit system):
414    cpus {
415      #size-cells = <0>;
416      #address-cells = <2>;
417
418      cpu@0 {
419        device_type = "cpu";
420        compatible = "arm,cortex-a57";
421        reg = <0x0 0x0>;
422        enable-method = "spin-table";
423        cpu-release-addr = <0 0x20000000>;
424      };
425
426      cpu@1 {
427        device_type = "cpu";
428        compatible = "arm,cortex-a57";
429        reg = <0x0 0x1>;
430        enable-method = "spin-table";
431        cpu-release-addr = <0 0x20000000>;
432      };
433
434      cpu@100 {
435        device_type = "cpu";
436        compatible = "arm,cortex-a57";
437        reg = <0x0 0x100>;
438        enable-method = "spin-table";
439        cpu-release-addr = <0 0x20000000>;
440      };
441
442      cpu@101 {
443        device_type = "cpu";
444        compatible = "arm,cortex-a57";
445        reg = <0x0 0x101>;
446        enable-method = "spin-table";
447        cpu-release-addr = <0 0x20000000>;
448      };
449
450      cpu@10000 {
451        device_type = "cpu";
452        compatible = "arm,cortex-a57";
453        reg = <0x0 0x10000>;
454        enable-method = "spin-table";
455        cpu-release-addr = <0 0x20000000>;
456      };
457
458      cpu@10001 {
459        device_type = "cpu";
460        compatible = "arm,cortex-a57";
461        reg = <0x0 0x10001>;
462        enable-method = "spin-table";
463        cpu-release-addr = <0 0x20000000>;
464      };
465
466      cpu@10100 {
467        device_type = "cpu";
468        compatible = "arm,cortex-a57";
469        reg = <0x0 0x10100>;
470        enable-method = "spin-table";
471        cpu-release-addr = <0 0x20000000>;
472      };
473
474      cpu@10101 {
475        device_type = "cpu";
476        compatible = "arm,cortex-a57";
477        reg = <0x0 0x10101>;
478        enable-method = "spin-table";
479        cpu-release-addr = <0 0x20000000>;
480      };
481
482      cpu@100000000 {
483        device_type = "cpu";
484        compatible = "arm,cortex-a57";
485        reg = <0x1 0x0>;
486        enable-method = "spin-table";
487        cpu-release-addr = <0 0x20000000>;
488      };
489
490      cpu@100000001 {
491        device_type = "cpu";
492        compatible = "arm,cortex-a57";
493        reg = <0x1 0x1>;
494        enable-method = "spin-table";
495        cpu-release-addr = <0 0x20000000>;
496      };
497
498      cpu@100000100 {
499        device_type = "cpu";
500        compatible = "arm,cortex-a57";
501        reg = <0x1 0x100>;
502        enable-method = "spin-table";
503        cpu-release-addr = <0 0x20000000>;
504      };
505
506      cpu@100000101 {
507        device_type = "cpu";
508        compatible = "arm,cortex-a57";
509        reg = <0x1 0x101>;
510        enable-method = "spin-table";
511        cpu-release-addr = <0 0x20000000>;
512      };
513
514      cpu@100010000 {
515        device_type = "cpu";
516        compatible = "arm,cortex-a57";
517        reg = <0x1 0x10000>;
518        enable-method = "spin-table";
519        cpu-release-addr = <0 0x20000000>;
520      };
521
522      cpu@100010001 {
523        device_type = "cpu";
524        compatible = "arm,cortex-a57";
525        reg = <0x1 0x10001>;
526        enable-method = "spin-table";
527        cpu-release-addr = <0 0x20000000>;
528      };
529
530      cpu@100010100 {
531        device_type = "cpu";
532        compatible = "arm,cortex-a57";
533        reg = <0x1 0x10100>;
534        enable-method = "spin-table";
535        cpu-release-addr = <0 0x20000000>;
536      };
537
538      cpu@100010101 {
539        device_type = "cpu";
540        compatible = "arm,cortex-a57";
541        reg = <0x1 0x10101>;
542        enable-method = "spin-table";
543        cpu-release-addr = <0 0x20000000>;
544      };
545    };
546...
547