1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a53
127      - arm,cortex-a57
128      - arm,cortex-a72
129      - arm,cortex-a73
130      - arm,cortex-m0
131      - arm,cortex-m0+
132      - arm,cortex-m1
133      - arm,cortex-m3
134      - arm,cortex-m4
135      - arm,cortex-r4
136      - arm,cortex-r5
137      - arm,cortex-r7
138      - brcm,brahma-b15
139      - brcm,brahma-b53
140      - brcm,vulcan
141      - cavium,thunder
142      - cavium,thunder2
143      - faraday,fa526
144      - intel,sa110
145      - intel,sa1100
146      - marvell,feroceon
147      - marvell,mohawk
148      - marvell,pj4a
149      - marvell,pj4b
150      - marvell,sheeva-v5
151      - marvell,sheeva-v7
152      - nvidia,tegra132-denver
153      - nvidia,tegra186-denver
154      - nvidia,tegra194-carmel
155      - qcom,krait
156      - qcom,kryo
157      - qcom,kryo385
158      - qcom,scorpion
159
160  enable-method:
161    allOf:
162      - $ref: '/schemas/types.yaml#/definitions/string'
163      - oneOf:
164          # On ARM v8 64-bit this property is required
165          - enum:
166              - psci
167              - spin-table
168          # On ARM 32-bit systems this property is optional
169          - enum:
170              - actions,s500-smp
171              - allwinner,sun6i-a31
172              - allwinner,sun8i-a23
173              - allwinner,sun9i-a80-smp
174              - allwinner,sun8i-a83t-smp
175              - amlogic,meson8-smp
176              - amlogic,meson8b-smp
177              - arm,realview-smp
178              - brcm,bcm11351-cpu-method
179              - brcm,bcm23550
180              - brcm,bcm2836-smp
181              - brcm,bcm63138
182              - brcm,bcm-nsp-smp
183              - brcm,brahma-b15
184              - marvell,armada-375-smp
185              - marvell,armada-380-smp
186              - marvell,armada-390-smp
187              - marvell,armada-xp-smp
188              - marvell,98dx3236-smp
189              - mediatek,mt6589-smp
190              - mediatek,mt81xx-tz-smp
191              - qcom,gcc-msm8660
192              - qcom,kpss-acc-v1
193              - qcom,kpss-acc-v2
194              - renesas,apmu
195              - renesas,r9a06g032-smp
196              - rockchip,rk3036-smp
197              - rockchip,rk3066-smp
198              - socionext,milbeaut-m10v-smp
199              - ste,dbx500-smp
200
201  cpu-release-addr:
202    $ref: '/schemas/types.yaml#/definitions/uint64'
203
204    description:
205      Required for systems that have an "enable-method"
206        property value of "spin-table".
207      On ARM v8 64-bit systems must be a two cell
208        property identifying a 64-bit zero-initialised
209        memory location.
210
211  cpu-idle-states:
212    $ref: '/schemas/types.yaml#/definitions/phandle-array'
213    description: |
214      List of phandles to idle state nodes supported
215      by this cpu (see ./idle-states.txt).
216
217  capacity-dmips-mhz:
218    $ref: '/schemas/types.yaml#/definitions/uint32'
219    description:
220      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
221      DMIPS/MHz, relative to highest capacity-dmips-mhz
222      in the system.
223
224  dynamic-power-coefficient:
225    $ref: '/schemas/types.yaml#/definitions/uint32'
226    description:
227      A u32 value that represents the running time dynamic
228      power coefficient in units of uW/MHz/V^2. The
229      coefficient can either be calculated from power
230      measurements or derived by analysis.
231
232      The dynamic power consumption of the CPU  is
233      proportional to the square of the Voltage (V) and
234      the clock frequency (f). The coefficient is used to
235      calculate the dynamic power as below -
236
237      Pdyn = dynamic-power-coefficient * V^2 * f
238
239      where voltage is in V, frequency is in MHz.
240
241  qcom,saw:
242    $ref: '/schemas/types.yaml#/definitions/phandle'
243    description: |
244      Specifies the SAW* node associated with this CPU.
245
246      Required for systems that have an "enable-method" property
247      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
248
249      * arm/msm/qcom,saw2.txt
250
251  qcom,acc:
252    $ref: '/schemas/types.yaml#/definitions/phandle'
253    description: |
254      Specifies the ACC* node associated with this CPU.
255
256      Required for systems that have an "enable-method" property
257      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
258
259      * arm/msm/qcom,kpss-acc.txt
260
261  rockchip,pmu:
262    $ref: '/schemas/types.yaml#/definitions/phandle'
263    description: |
264      Specifies the syscon node controlling the cpu core power domains.
265
266      Optional for systems that have an "enable-method"
267      property value of "rockchip,rk3066-smp"
268      While optional, it is the preferred way to get access to
269      the cpu-core power-domains.
270
271required:
272  - device_type
273  - reg
274  - compatible
275
276dependencies:
277  rockchip,pmu: [enable-method]
278
279examples:
280  - |
281    cpus {
282      #size-cells = <0>;
283      #address-cells = <1>;
284
285      cpu@0 {
286        device_type = "cpu";
287        compatible = "arm,cortex-a15";
288        reg = <0x0>;
289      };
290
291      cpu@1 {
292        device_type = "cpu";
293        compatible = "arm,cortex-a15";
294        reg = <0x1>;
295      };
296
297      cpu@100 {
298        device_type = "cpu";
299        compatible = "arm,cortex-a7";
300        reg = <0x100>;
301      };
302
303      cpu@101 {
304        device_type = "cpu";
305        compatible = "arm,cortex-a7";
306        reg = <0x101>;
307      };
308    };
309
310  - |
311    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
312    cpus {
313      #size-cells = <0>;
314      #address-cells = <1>;
315
316      cpu@0 {
317        device_type = "cpu";
318        compatible = "arm,cortex-a8";
319        reg = <0x0>;
320      };
321    };
322
323  - |
324    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
325    cpus {
326      #size-cells = <0>;
327      #address-cells = <1>;
328
329      cpu@0 {
330        device_type = "cpu";
331        compatible = "arm,arm926ej-s";
332        reg = <0x0>;
333      };
334    };
335
336  - |
337    //  Example 4 (ARM Cortex-A57 64-bit system):
338    cpus {
339      #size-cells = <0>;
340      #address-cells = <2>;
341
342      cpu@0 {
343        device_type = "cpu";
344        compatible = "arm,cortex-a57";
345        reg = <0x0 0x0>;
346        enable-method = "spin-table";
347        cpu-release-addr = <0 0x20000000>;
348      };
349
350      cpu@1 {
351        device_type = "cpu";
352        compatible = "arm,cortex-a57";
353        reg = <0x0 0x1>;
354        enable-method = "spin-table";
355        cpu-release-addr = <0 0x20000000>;
356      };
357
358      cpu@100 {
359        device_type = "cpu";
360        compatible = "arm,cortex-a57";
361        reg = <0x0 0x100>;
362        enable-method = "spin-table";
363        cpu-release-addr = <0 0x20000000>;
364      };
365
366      cpu@101 {
367        device_type = "cpu";
368        compatible = "arm,cortex-a57";
369        reg = <0x0 0x101>;
370        enable-method = "spin-table";
371        cpu-release-addr = <0 0x20000000>;
372      };
373
374      cpu@10000 {
375        device_type = "cpu";
376        compatible = "arm,cortex-a57";
377        reg = <0x0 0x10000>;
378        enable-method = "spin-table";
379        cpu-release-addr = <0 0x20000000>;
380      };
381
382      cpu@10001 {
383        device_type = "cpu";
384        compatible = "arm,cortex-a57";
385        reg = <0x0 0x10001>;
386        enable-method = "spin-table";
387        cpu-release-addr = <0 0x20000000>;
388      };
389
390      cpu@10100 {
391        device_type = "cpu";
392        compatible = "arm,cortex-a57";
393        reg = <0x0 0x10100>;
394        enable-method = "spin-table";
395        cpu-release-addr = <0 0x20000000>;
396      };
397
398      cpu@10101 {
399        device_type = "cpu";
400        compatible = "arm,cortex-a57";
401        reg = <0x0 0x10101>;
402        enable-method = "spin-table";
403        cpu-release-addr = <0 0x20000000>;
404      };
405
406      cpu@100000000 {
407        device_type = "cpu";
408        compatible = "arm,cortex-a57";
409        reg = <0x1 0x0>;
410        enable-method = "spin-table";
411        cpu-release-addr = <0 0x20000000>;
412      };
413
414      cpu@100000001 {
415        device_type = "cpu";
416        compatible = "arm,cortex-a57";
417        reg = <0x1 0x1>;
418        enable-method = "spin-table";
419        cpu-release-addr = <0 0x20000000>;
420      };
421
422      cpu@100000100 {
423        device_type = "cpu";
424        compatible = "arm,cortex-a57";
425        reg = <0x1 0x100>;
426        enable-method = "spin-table";
427        cpu-release-addr = <0 0x20000000>;
428      };
429
430      cpu@100000101 {
431        device_type = "cpu";
432        compatible = "arm,cortex-a57";
433        reg = <0x1 0x101>;
434        enable-method = "spin-table";
435        cpu-release-addr = <0 0x20000000>;
436      };
437
438      cpu@100010000 {
439        device_type = "cpu";
440        compatible = "arm,cortex-a57";
441        reg = <0x1 0x10000>;
442        enable-method = "spin-table";
443        cpu-release-addr = <0 0x20000000>;
444      };
445
446      cpu@100010001 {
447        device_type = "cpu";
448        compatible = "arm,cortex-a57";
449        reg = <0x1 0x10001>;
450        enable-method = "spin-table";
451        cpu-release-addr = <0 0x20000000>;
452      };
453
454      cpu@100010100 {
455        device_type = "cpu";
456        compatible = "arm,cortex-a57";
457        reg = <0x1 0x10100>;
458        enable-method = "spin-table";
459        cpu-release-addr = <0 0x20000000>;
460      };
461
462      cpu@100010101 {
463        device_type = "cpu";
464        compatible = "arm,cortex-a57";
465        reg = <0x1 0x10101>;
466        enable-method = "spin-table";
467        cpu-release-addr = <0 0x20000000>;
468      };
469    };
470...
471