1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,avalanche
89      - apple,blizzard
90      - apple,icestorm
91      - apple,firestorm
92      - arm,arm710t
93      - arm,arm720t
94      - arm,arm740t
95      - arm,arm7ej-s
96      - arm,arm7tdmi
97      - arm,arm7tdmi-s
98      - arm,arm9es
99      - arm,arm9ej-s
100      - arm,arm920t
101      - arm,arm922t
102      - arm,arm925
103      - arm,arm926e-s
104      - arm,arm926ej-s
105      - arm,arm940t
106      - arm,arm946e-s
107      - arm,arm966e-s
108      - arm,arm968e-s
109      - arm,arm9tdmi
110      - arm,arm1020e
111      - arm,arm1020t
112      - arm,arm1022e
113      - arm,arm1026ej-s
114      - arm,arm1136j-s
115      - arm,arm1136jf-s
116      - arm,arm1156t2-s
117      - arm,arm1156t2f-s
118      - arm,arm1176jzf
119      - arm,arm1176jz-s
120      - arm,arm1176jzf-s
121      - arm,arm11mpcore
122      - arm,armv8 # Only for s/w models
123      - arm,cortex-a5
124      - arm,cortex-a7
125      - arm,cortex-a8
126      - arm,cortex-a9
127      - arm,cortex-a12
128      - arm,cortex-a15
129      - arm,cortex-a17
130      - arm,cortex-a32
131      - arm,cortex-a34
132      - arm,cortex-a35
133      - arm,cortex-a53
134      - arm,cortex-a55
135      - arm,cortex-a57
136      - arm,cortex-a65
137      - arm,cortex-a72
138      - arm,cortex-a73
139      - arm,cortex-a75
140      - arm,cortex-a76
141      - arm,cortex-a77
142      - arm,cortex-a78
143      - arm,cortex-a78ae
144      - arm,cortex-a78c
145      - arm,cortex-a510
146      - arm,cortex-a710
147      - arm,cortex-a715
148      - arm,cortex-m0
149      - arm,cortex-m0+
150      - arm,cortex-m1
151      - arm,cortex-m3
152      - arm,cortex-m4
153      - arm,cortex-r4
154      - arm,cortex-r5
155      - arm,cortex-r7
156      - arm,cortex-r52
157      - arm,cortex-x1
158      - arm,cortex-x1c
159      - arm,cortex-x2
160      - arm,cortex-x3
161      - arm,neoverse-e1
162      - arm,neoverse-n1
163      - arm,neoverse-n2
164      - arm,neoverse-v1
165      - brcm,brahma-b15
166      - brcm,brahma-b53
167      - brcm,vulcan
168      - cavium,thunder
169      - cavium,thunder2
170      - faraday,fa526
171      - intel,sa110
172      - intel,sa1100
173      - marvell,feroceon
174      - marvell,mohawk
175      - marvell,pj4a
176      - marvell,pj4b
177      - marvell,sheeva-v5
178      - marvell,sheeva-v7
179      - nvidia,tegra132-denver
180      - nvidia,tegra186-denver
181      - nvidia,tegra194-carmel
182      - qcom,krait
183      - qcom,kryo
184      - qcom,kryo240
185      - qcom,kryo250
186      - qcom,kryo260
187      - qcom,kryo280
188      - qcom,kryo360
189      - qcom,kryo385
190      - qcom,kryo468
191      - qcom,kryo485
192      - qcom,kryo560
193      - qcom,kryo570
194      - qcom,kryo660
195      - qcom,kryo685
196      - qcom,kryo780
197      - qcom,scorpion
198
199  enable-method:
200    $ref: /schemas/types.yaml#/definitions/string
201    oneOf:
202      # On ARM v8 64-bit this property is required
203      - enum:
204          - psci
205          - spin-table
206      # On ARM 32-bit systems this property is optional
207      - enum:
208          - actions,s500-smp
209          - allwinner,sun6i-a31
210          - allwinner,sun8i-a23
211          - allwinner,sun9i-a80-smp
212          - allwinner,sun8i-a83t-smp
213          - amlogic,meson8-smp
214          - amlogic,meson8b-smp
215          - arm,realview-smp
216          - aspeed,ast2600-smp
217          - brcm,bcm11351-cpu-method
218          - brcm,bcm23550
219          - brcm,bcm2836-smp
220          - brcm,bcm63138
221          - brcm,bcm-nsp-smp
222          - brcm,brahma-b15
223          - marvell,armada-375-smp
224          - marvell,armada-380-smp
225          - marvell,armada-390-smp
226          - marvell,armada-xp-smp
227          - marvell,98dx3236-smp
228          - marvell,mmp3-smp
229          - mediatek,mt6589-smp
230          - mediatek,mt81xx-tz-smp
231          - qcom,gcc-msm8660
232          - qcom,kpss-acc-v1
233          - qcom,kpss-acc-v2
234          - qcom,msm8226-smp
235          - qcom,msm8909-smp
236          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
237          - qcom,msm8916-smp
238          - renesas,apmu
239          - renesas,r9a06g032-smp
240          - rockchip,rk3036-smp
241          - rockchip,rk3066-smp
242          - socionext,milbeaut-m10v-smp
243          - ste,dbx500-smp
244          - ti,am3352
245          - ti,am4372
246
247  cpu-release-addr:
248    oneOf:
249      - $ref: /schemas/types.yaml#/definitions/uint32
250      - $ref: /schemas/types.yaml#/definitions/uint64
251    description:
252      The DT specification defines this as 64-bit always, but some 32-bit Arm
253      systems have used a 32-bit value which must be supported.
254      Required for systems that have an "enable-method"
255        property value of "spin-table".
256
257  cpu-idle-states:
258    $ref: /schemas/types.yaml#/definitions/phandle-array
259    items:
260      maxItems: 1
261    description: |
262      List of phandles to idle state nodes supported
263      by this cpu (see ./idle-states.yaml).
264
265  capacity-dmips-mhz:
266    description:
267      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
268      DMIPS/MHz, relative to highest capacity-dmips-mhz
269      in the system.
270
271  cci-control-port: true
272
273  dynamic-power-coefficient:
274    $ref: /schemas/types.yaml#/definitions/uint32
275    description:
276      A u32 value that represents the running time dynamic
277      power coefficient in units of uW/MHz/V^2. The
278      coefficient can either be calculated from power
279      measurements or derived by analysis.
280
281      The dynamic power consumption of the CPU  is
282      proportional to the square of the Voltage (V) and
283      the clock frequency (f). The coefficient is used to
284      calculate the dynamic power as below -
285
286      Pdyn = dynamic-power-coefficient * V^2 * f
287
288      where voltage is in V, frequency is in MHz.
289
290  performance-domains:
291    maxItems: 1
292    description:
293      List of phandles and performance domain specifiers, as defined by
294      bindings of the performance domain provider. See also
295      dvfs/performance-domain.yaml.
296
297  power-domains:
298    description:
299      List of phandles and PM domain specifiers, as defined by bindings of the
300      PM domain provider (see also ../power_domain.txt).
301
302  power-domain-names:
303    description:
304      A list of power domain name strings sorted in the same order as the
305      power-domains property.
306
307      For PSCI based platforms, the name corresponding to the index of the PSCI
308      PM domain provider, must be "psci".
309
310  qcom,saw:
311    $ref: /schemas/types.yaml#/definitions/phandle
312    description: |
313      Specifies the SAW* node associated with this CPU.
314
315      Required for systems that have an "enable-method" property
316      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
317
318      * arm/msm/qcom,saw2.txt
319
320  qcom,acc:
321    $ref: /schemas/types.yaml#/definitions/phandle
322    description: |
323      Specifies the ACC* node associated with this CPU.
324
325      Required for systems that have an "enable-method" property
326      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
327      "qcom,msm8916-smp".
328
329      * arm/msm/qcom,kpss-acc.txt
330
331  rockchip,pmu:
332    $ref: /schemas/types.yaml#/definitions/phandle
333    description: |
334      Specifies the syscon node controlling the cpu core power domains.
335
336      Optional for systems that have an "enable-method"
337      property value of "rockchip,rk3066-smp"
338      While optional, it is the preferred way to get access to
339      the cpu-core power-domains.
340
341  secondary-boot-reg:
342    $ref: /schemas/types.yaml#/definitions/uint32
343    description: |
344      Required for systems that have an "enable-method" property value of
345      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
346
347      This includes the following SoCs: |
348      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
349      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
350
351      The secondary-boot-reg property is a u32 value that specifies the
352      physical address of the register used to request the ROM holding pen
353      code release a secondary CPU. The value written to the register is
354      formed by encoding the target CPU id into the low bits of the
355      physical start address it should jump to.
356
357if:
358  # If the enable-method property contains one of those values
359  properties:
360    enable-method:
361      contains:
362        enum:
363          - brcm,bcm11351-cpu-method
364          - brcm,bcm23550
365          - brcm,bcm-nsp-smp
366  # and if enable-method is present
367  required:
368    - enable-method
369
370then:
371  required:
372    - secondary-boot-reg
373
374required:
375  - device_type
376  - reg
377  - compatible
378
379dependencies:
380  rockchip,pmu: [enable-method]
381
382additionalProperties: true
383
384examples:
385  - |
386    cpus {
387      #size-cells = <0>;
388      #address-cells = <1>;
389
390      cpu@0 {
391        device_type = "cpu";
392        compatible = "arm,cortex-a15";
393        reg = <0x0>;
394      };
395
396      cpu@1 {
397        device_type = "cpu";
398        compatible = "arm,cortex-a15";
399        reg = <0x1>;
400      };
401
402      cpu@100 {
403        device_type = "cpu";
404        compatible = "arm,cortex-a7";
405        reg = <0x100>;
406      };
407
408      cpu@101 {
409        device_type = "cpu";
410        compatible = "arm,cortex-a7";
411        reg = <0x101>;
412      };
413    };
414
415  - |
416    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
417    cpus {
418      #size-cells = <0>;
419      #address-cells = <1>;
420
421      cpu@0 {
422        device_type = "cpu";
423        compatible = "arm,cortex-a8";
424        reg = <0x0>;
425      };
426    };
427
428  - |
429    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
430    cpus {
431      #size-cells = <0>;
432      #address-cells = <1>;
433
434      cpu@0 {
435        device_type = "cpu";
436        compatible = "arm,arm926ej-s";
437        reg = <0x0>;
438      };
439    };
440
441  - |
442    //  Example 4 (ARM Cortex-A57 64-bit system):
443    cpus {
444      #size-cells = <0>;
445      #address-cells = <2>;
446
447      cpu@0 {
448        device_type = "cpu";
449        compatible = "arm,cortex-a57";
450        reg = <0x0 0x0>;
451        enable-method = "spin-table";
452        cpu-release-addr = <0 0x20000000>;
453      };
454
455      cpu@1 {
456        device_type = "cpu";
457        compatible = "arm,cortex-a57";
458        reg = <0x0 0x1>;
459        enable-method = "spin-table";
460        cpu-release-addr = <0 0x20000000>;
461      };
462
463      cpu@100 {
464        device_type = "cpu";
465        compatible = "arm,cortex-a57";
466        reg = <0x0 0x100>;
467        enable-method = "spin-table";
468        cpu-release-addr = <0 0x20000000>;
469      };
470
471      cpu@101 {
472        device_type = "cpu";
473        compatible = "arm,cortex-a57";
474        reg = <0x0 0x101>;
475        enable-method = "spin-table";
476        cpu-release-addr = <0 0x20000000>;
477      };
478
479      cpu@10000 {
480        device_type = "cpu";
481        compatible = "arm,cortex-a57";
482        reg = <0x0 0x10000>;
483        enable-method = "spin-table";
484        cpu-release-addr = <0 0x20000000>;
485      };
486
487      cpu@10001 {
488        device_type = "cpu";
489        compatible = "arm,cortex-a57";
490        reg = <0x0 0x10001>;
491        enable-method = "spin-table";
492        cpu-release-addr = <0 0x20000000>;
493      };
494
495      cpu@10100 {
496        device_type = "cpu";
497        compatible = "arm,cortex-a57";
498        reg = <0x0 0x10100>;
499        enable-method = "spin-table";
500        cpu-release-addr = <0 0x20000000>;
501      };
502
503      cpu@10101 {
504        device_type = "cpu";
505        compatible = "arm,cortex-a57";
506        reg = <0x0 0x10101>;
507        enable-method = "spin-table";
508        cpu-release-addr = <0 0x20000000>;
509      };
510
511      cpu@100000000 {
512        device_type = "cpu";
513        compatible = "arm,cortex-a57";
514        reg = <0x1 0x0>;
515        enable-method = "spin-table";
516        cpu-release-addr = <0 0x20000000>;
517      };
518
519      cpu@100000001 {
520        device_type = "cpu";
521        compatible = "arm,cortex-a57";
522        reg = <0x1 0x1>;
523        enable-method = "spin-table";
524        cpu-release-addr = <0 0x20000000>;
525      };
526
527      cpu@100000100 {
528        device_type = "cpu";
529        compatible = "arm,cortex-a57";
530        reg = <0x1 0x100>;
531        enable-method = "spin-table";
532        cpu-release-addr = <0 0x20000000>;
533      };
534
535      cpu@100000101 {
536        device_type = "cpu";
537        compatible = "arm,cortex-a57";
538        reg = <0x1 0x101>;
539        enable-method = "spin-table";
540        cpu-release-addr = <0 0x20000000>;
541      };
542
543      cpu@100010000 {
544        device_type = "cpu";
545        compatible = "arm,cortex-a57";
546        reg = <0x1 0x10000>;
547        enable-method = "spin-table";
548        cpu-release-addr = <0 0x20000000>;
549      };
550
551      cpu@100010001 {
552        device_type = "cpu";
553        compatible = "arm,cortex-a57";
554        reg = <0x1 0x10001>;
555        enable-method = "spin-table";
556        cpu-release-addr = <0 0x20000000>;
557      };
558
559      cpu@100010100 {
560        device_type = "cpu";
561        compatible = "arm,cortex-a57";
562        reg = <0x1 0x10100>;
563        enable-method = "spin-table";
564        cpu-release-addr = <0 0x20000000>;
565      };
566
567      cpu@100010101 {
568        device_type = "cpu";
569        compatible = "arm,cortex-a57";
570        reg = <0x1 0x10101>;
571        enable-method = "spin-table";
572        cpu-release-addr = <0 0x20000000>;
573      };
574    };
575...
576