1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a32
127      - arm,cortex-a34
128      - arm,cortex-a35
129      - arm,cortex-a53
130      - arm,cortex-a55
131      - arm,cortex-a57
132      - arm,cortex-a65
133      - arm,cortex-a72
134      - arm,cortex-a73
135      - arm,cortex-a75
136      - arm,cortex-a76
137      - arm,cortex-a77
138      - arm,cortex-m0
139      - arm,cortex-m0+
140      - arm,cortex-m1
141      - arm,cortex-m3
142      - arm,cortex-m4
143      - arm,cortex-r4
144      - arm,cortex-r5
145      - arm,cortex-r7
146      - arm,neoverse-e1
147      - arm,neoverse-n1
148      - brcm,brahma-b15
149      - brcm,brahma-b53
150      - brcm,vulcan
151      - cavium,thunder
152      - cavium,thunder2
153      - faraday,fa526
154      - intel,sa110
155      - intel,sa1100
156      - marvell,feroceon
157      - marvell,mohawk
158      - marvell,pj4a
159      - marvell,pj4b
160      - marvell,sheeva-v5
161      - marvell,sheeva-v7
162      - nvidia,tegra132-denver
163      - nvidia,tegra186-denver
164      - nvidia,tegra194-carmel
165      - qcom,krait
166      - qcom,kryo
167      - qcom,kryo260
168      - qcom,kryo280
169      - qcom,kryo385
170      - qcom,kryo485
171      - qcom,scorpion
172
173  enable-method:
174    $ref: '/schemas/types.yaml#/definitions/string'
175    oneOf:
176      # On ARM v8 64-bit this property is required
177      - enum:
178          - psci
179          - spin-table
180      # On ARM 32-bit systems this property is optional
181      - enum:
182          - actions,s500-smp
183          - allwinner,sun6i-a31
184          - allwinner,sun8i-a23
185          - allwinner,sun9i-a80-smp
186          - allwinner,sun8i-a83t-smp
187          - amlogic,meson8-smp
188          - amlogic,meson8b-smp
189          - arm,realview-smp
190          - aspeed,ast2600-smp
191          - brcm,bcm11351-cpu-method
192          - brcm,bcm23550
193          - brcm,bcm2836-smp
194          - brcm,bcm63138
195          - brcm,bcm-nsp-smp
196          - brcm,brahma-b15
197          - marvell,armada-375-smp
198          - marvell,armada-380-smp
199          - marvell,armada-390-smp
200          - marvell,armada-xp-smp
201          - marvell,98dx3236-smp
202          - marvell,mmp3-smp
203          - mediatek,mt6589-smp
204          - mediatek,mt81xx-tz-smp
205          - qcom,gcc-msm8660
206          - qcom,kpss-acc-v1
207          - qcom,kpss-acc-v2
208          - renesas,apmu
209          - renesas,r9a06g032-smp
210          - rockchip,rk3036-smp
211          - rockchip,rk3066-smp
212          - socionext,milbeaut-m10v-smp
213          - ste,dbx500-smp
214          - ti,am3352
215          - ti,am4372
216
217  cpu-release-addr:
218    $ref: '/schemas/types.yaml#/definitions/uint64'
219
220    description:
221      Required for systems that have an "enable-method"
222        property value of "spin-table".
223      On ARM v8 64-bit systems must be a two cell
224        property identifying a 64-bit zero-initialised
225        memory location.
226
227  cpu-idle-states:
228    $ref: '/schemas/types.yaml#/definitions/phandle-array'
229    description: |
230      List of phandles to idle state nodes supported
231      by this cpu (see ./idle-states.yaml).
232
233  capacity-dmips-mhz:
234    $ref: '/schemas/types.yaml#/definitions/uint32'
235    description:
236      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
237      DMIPS/MHz, relative to highest capacity-dmips-mhz
238      in the system.
239
240  dynamic-power-coefficient:
241    $ref: '/schemas/types.yaml#/definitions/uint32'
242    description:
243      A u32 value that represents the running time dynamic
244      power coefficient in units of uW/MHz/V^2. The
245      coefficient can either be calculated from power
246      measurements or derived by analysis.
247
248      The dynamic power consumption of the CPU  is
249      proportional to the square of the Voltage (V) and
250      the clock frequency (f). The coefficient is used to
251      calculate the dynamic power as below -
252
253      Pdyn = dynamic-power-coefficient * V^2 * f
254
255      where voltage is in V, frequency is in MHz.
256
257  power-domains:
258    $ref: '/schemas/types.yaml#/definitions/phandle-array'
259    description:
260      List of phandles and PM domain specifiers, as defined by bindings of the
261      PM domain provider (see also ../power_domain.txt).
262
263  power-domain-names:
264    $ref: '/schemas/types.yaml#/definitions/string-array'
265    description:
266      A list of power domain name strings sorted in the same order as the
267      power-domains property.
268
269      For PSCI based platforms, the name corresponding to the index of the PSCI
270      PM domain provider, must be "psci".
271
272  qcom,saw:
273    $ref: '/schemas/types.yaml#/definitions/phandle'
274    description: |
275      Specifies the SAW* node associated with this CPU.
276
277      Required for systems that have an "enable-method" property
278      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
279
280      * arm/msm/qcom,saw2.txt
281
282  qcom,acc:
283    $ref: '/schemas/types.yaml#/definitions/phandle'
284    description: |
285      Specifies the ACC* node associated with this CPU.
286
287      Required for systems that have an "enable-method" property
288      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
289
290      * arm/msm/qcom,kpss-acc.txt
291
292  rockchip,pmu:
293    $ref: '/schemas/types.yaml#/definitions/phandle'
294    description: |
295      Specifies the syscon node controlling the cpu core power domains.
296
297      Optional for systems that have an "enable-method"
298      property value of "rockchip,rk3066-smp"
299      While optional, it is the preferred way to get access to
300      the cpu-core power-domains.
301
302  secondary-boot-reg:
303    $ref: '/schemas/types.yaml#/definitions/uint32'
304    description: |
305      Required for systems that have an "enable-method" property value of
306      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
307
308      This includes the following SoCs: |
309      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
310      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
311
312      The secondary-boot-reg property is a u32 value that specifies the
313      physical address of the register used to request the ROM holding pen
314      code release a secondary CPU. The value written to the register is
315      formed by encoding the target CPU id into the low bits of the
316      physical start address it should jump to.
317
318if:
319  # If the enable-method property contains one of those values
320  properties:
321    enable-method:
322      contains:
323        enum:
324          - brcm,bcm11351-cpu-method
325          - brcm,bcm23550
326          - brcm,bcm-nsp-smp
327  # and if enable-method is present
328  required:
329    - enable-method
330
331then:
332   required:
333     - secondary-boot-reg
334
335required:
336  - device_type
337  - reg
338  - compatible
339
340dependencies:
341  rockchip,pmu: [enable-method]
342
343examples:
344  - |
345    cpus {
346      #size-cells = <0>;
347      #address-cells = <1>;
348
349      cpu@0 {
350        device_type = "cpu";
351        compatible = "arm,cortex-a15";
352        reg = <0x0>;
353      };
354
355      cpu@1 {
356        device_type = "cpu";
357        compatible = "arm,cortex-a15";
358        reg = <0x1>;
359      };
360
361      cpu@100 {
362        device_type = "cpu";
363        compatible = "arm,cortex-a7";
364        reg = <0x100>;
365      };
366
367      cpu@101 {
368        device_type = "cpu";
369        compatible = "arm,cortex-a7";
370        reg = <0x101>;
371      };
372    };
373
374  - |
375    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
376    cpus {
377      #size-cells = <0>;
378      #address-cells = <1>;
379
380      cpu@0 {
381        device_type = "cpu";
382        compatible = "arm,cortex-a8";
383        reg = <0x0>;
384      };
385    };
386
387  - |
388    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
389    cpus {
390      #size-cells = <0>;
391      #address-cells = <1>;
392
393      cpu@0 {
394        device_type = "cpu";
395        compatible = "arm,arm926ej-s";
396        reg = <0x0>;
397      };
398    };
399
400  - |
401    //  Example 4 (ARM Cortex-A57 64-bit system):
402    cpus {
403      #size-cells = <0>;
404      #address-cells = <2>;
405
406      cpu@0 {
407        device_type = "cpu";
408        compatible = "arm,cortex-a57";
409        reg = <0x0 0x0>;
410        enable-method = "spin-table";
411        cpu-release-addr = <0 0x20000000>;
412      };
413
414      cpu@1 {
415        device_type = "cpu";
416        compatible = "arm,cortex-a57";
417        reg = <0x0 0x1>;
418        enable-method = "spin-table";
419        cpu-release-addr = <0 0x20000000>;
420      };
421
422      cpu@100 {
423        device_type = "cpu";
424        compatible = "arm,cortex-a57";
425        reg = <0x0 0x100>;
426        enable-method = "spin-table";
427        cpu-release-addr = <0 0x20000000>;
428      };
429
430      cpu@101 {
431        device_type = "cpu";
432        compatible = "arm,cortex-a57";
433        reg = <0x0 0x101>;
434        enable-method = "spin-table";
435        cpu-release-addr = <0 0x20000000>;
436      };
437
438      cpu@10000 {
439        device_type = "cpu";
440        compatible = "arm,cortex-a57";
441        reg = <0x0 0x10000>;
442        enable-method = "spin-table";
443        cpu-release-addr = <0 0x20000000>;
444      };
445
446      cpu@10001 {
447        device_type = "cpu";
448        compatible = "arm,cortex-a57";
449        reg = <0x0 0x10001>;
450        enable-method = "spin-table";
451        cpu-release-addr = <0 0x20000000>;
452      };
453
454      cpu@10100 {
455        device_type = "cpu";
456        compatible = "arm,cortex-a57";
457        reg = <0x0 0x10100>;
458        enable-method = "spin-table";
459        cpu-release-addr = <0 0x20000000>;
460      };
461
462      cpu@10101 {
463        device_type = "cpu";
464        compatible = "arm,cortex-a57";
465        reg = <0x0 0x10101>;
466        enable-method = "spin-table";
467        cpu-release-addr = <0 0x20000000>;
468      };
469
470      cpu@100000000 {
471        device_type = "cpu";
472        compatible = "arm,cortex-a57";
473        reg = <0x1 0x0>;
474        enable-method = "spin-table";
475        cpu-release-addr = <0 0x20000000>;
476      };
477
478      cpu@100000001 {
479        device_type = "cpu";
480        compatible = "arm,cortex-a57";
481        reg = <0x1 0x1>;
482        enable-method = "spin-table";
483        cpu-release-addr = <0 0x20000000>;
484      };
485
486      cpu@100000100 {
487        device_type = "cpu";
488        compatible = "arm,cortex-a57";
489        reg = <0x1 0x100>;
490        enable-method = "spin-table";
491        cpu-release-addr = <0 0x20000000>;
492      };
493
494      cpu@100000101 {
495        device_type = "cpu";
496        compatible = "arm,cortex-a57";
497        reg = <0x1 0x101>;
498        enable-method = "spin-table";
499        cpu-release-addr = <0 0x20000000>;
500      };
501
502      cpu@100010000 {
503        device_type = "cpu";
504        compatible = "arm,cortex-a57";
505        reg = <0x1 0x10000>;
506        enable-method = "spin-table";
507        cpu-release-addr = <0 0x20000000>;
508      };
509
510      cpu@100010001 {
511        device_type = "cpu";
512        compatible = "arm,cortex-a57";
513        reg = <0x1 0x10001>;
514        enable-method = "spin-table";
515        cpu-release-addr = <0 0x20000000>;
516      };
517
518      cpu@100010100 {
519        device_type = "cpu";
520        compatible = "arm,cortex-a57";
521        reg = <0x1 0x10100>;
522        enable-method = "spin-table";
523        cpu-release-addr = <0 0x20000000>;
524      };
525
526      cpu@100010101 {
527        device_type = "cpu";
528        compatible = "arm,cortex-a57";
529        reg = <0x1 0x10101>;
530        enable-method = "spin-table";
531        cpu-release-addr = <0 0x20000000>;
532      };
533    };
534...
535