1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs bindings 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 $nodename: 43 const: cpus 44 description: Container of cpu nodes 45 46 '#address-cells': 47 enum: [1, 2] 48 description: | 49 Definition depends on ARM architecture version and configuration: 50 51 On uniprocessor ARM architectures previous to v7 52 value must be 1, to enable a simple enumeration 53 scheme for processors that do not have a HW CPU 54 identification register. 55 On 32-bit ARM 11 MPcore, ARM v7 or later systems 56 value must be 1, that corresponds to CPUID/MPIDR 57 registers sizes. 58 On ARM v8 64-bit systems value should be set to 2, 59 that corresponds to the MPIDR_EL1 register size. 60 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 61 in the system, #address-cells can be set to 1, since 62 MPIDR_EL1[63:32] bits are not used for CPUs 63 identification. 64 65 '#size-cells': 66 const: 0 67 68patternProperties: 69 '^cpu@[0-9a-f]+$': 70 type: object 71 properties: 72 device_type: 73 const: cpu 74 75 reg: 76 maxItems: 1 77 description: | 78 Usage and definition depend on ARM architecture version and 79 configuration: 80 81 On uniprocessor ARM architectures previous to v7 82 this property is required and must be set to 0. 83 84 On ARM 11 MPcore based systems this property is 85 required and matches the CPUID[11:0] register bits. 86 87 Bits [11:0] in the reg cell must be set to 88 bits [11:0] in CPU ID register. 89 90 All other bits in the reg cell must be set to 0. 91 92 On 32-bit ARM v7 or later systems this property is 93 required and matches the CPU MPIDR[23:0] register 94 bits. 95 96 Bits [23:0] in the reg cell must be set to 97 bits [23:0] in MPIDR. 98 99 All other bits in the reg cell must be set to 0. 100 101 On ARM v8 64-bit systems this property is required 102 and matches the MPIDR_EL1 register affinity bits. 103 104 * If cpus node's #address-cells property is set to 2 105 106 The first reg cell bits [7:0] must be set to 107 bits [39:32] of MPIDR_EL1. 108 109 The second reg cell bits [23:0] must be set to 110 bits [23:0] of MPIDR_EL1. 111 112 * If cpus node's #address-cells property is set to 1 113 114 The reg cell bits [23:0] must be set to bits [23:0] 115 of MPIDR_EL1. 116 117 All other bits in the reg cells must be set to 0. 118 119 compatible: 120 items: 121 - enum: 122 - arm,arm710t 123 - arm,arm720t 124 - arm,arm740t 125 - arm,arm7ej-s 126 - arm,arm7tdmi 127 - arm,arm7tdmi-s 128 - arm,arm9es 129 - arm,arm9ej-s 130 - arm,arm920t 131 - arm,arm922t 132 - arm,arm925 133 - arm,arm926e-s 134 - arm,arm926ej-s 135 - arm,arm940t 136 - arm,arm946e-s 137 - arm,arm966e-s 138 - arm,arm968e-s 139 - arm,arm9tdmi 140 - arm,arm1020e 141 - arm,arm1020t 142 - arm,arm1022e 143 - arm,arm1026ej-s 144 - arm,arm1136j-s 145 - arm,arm1136jf-s 146 - arm,arm1156t2-s 147 - arm,arm1156t2f-s 148 - arm,arm1176jzf 149 - arm,arm1176jz-s 150 - arm,arm1176jzf-s 151 - arm,arm11mpcore 152 - arm,armv8 # Only for s/w models 153 - arm,cortex-a5 154 - arm,cortex-a7 155 - arm,cortex-a8 156 - arm,cortex-a9 157 - arm,cortex-a12 158 - arm,cortex-a15 159 - arm,cortex-a17 160 - arm,cortex-a53 161 - arm,cortex-a57 162 - arm,cortex-a72 163 - arm,cortex-a73 164 - arm,cortex-m0 165 - arm,cortex-m0+ 166 - arm,cortex-m1 167 - arm,cortex-m3 168 - arm,cortex-m4 169 - arm,cortex-r4 170 - arm,cortex-r5 171 - arm,cortex-r7 172 - brcm,brahma-b15 173 - brcm,brahma-b53 174 - brcm,vulcan 175 - cavium,thunder 176 - cavium,thunder2 177 - faraday,fa526 178 - intel,sa110 179 - intel,sa1100 180 - marvell,feroceon 181 - marvell,mohawk 182 - marvell,pj4a 183 - marvell,pj4b 184 - marvell,sheeva-v5 185 - marvell,sheeva-v7 186 - nvidia,tegra132-denver 187 - nvidia,tegra186-denver 188 - nvidia,tegra194-carmel 189 - qcom,krait 190 - qcom,kryo 191 - qcom,kryo385 192 - qcom,scorpion 193 194 enable-method: 195 allOf: 196 - $ref: '/schemas/types.yaml#/definitions/string' 197 - oneOf: 198 # On ARM v8 64-bit this property is required 199 - enum: 200 - psci 201 - spin-table 202 # On ARM 32-bit systems this property is optional 203 - enum: 204 - actions,s500-smp 205 - allwinner,sun6i-a31 206 - allwinner,sun8i-a23 207 - allwinner,sun9i-a80-smp 208 - allwinner,sun8i-a83t-smp 209 - amlogic,meson8-smp 210 - amlogic,meson8b-smp 211 - arm,realview-smp 212 - brcm,bcm11351-cpu-method 213 - brcm,bcm23550 214 - brcm,bcm2836-smp 215 - brcm,bcm63138 216 - brcm,bcm-nsp-smp 217 - brcm,brahma-b15 218 - marvell,armada-375-smp 219 - marvell,armada-380-smp 220 - marvell,armada-390-smp 221 - marvell,armada-xp-smp 222 - marvell,98dx3236-smp 223 - mediatek,mt6589-smp 224 - mediatek,mt81xx-tz-smp 225 - qcom,gcc-msm8660 226 - qcom,kpss-acc-v1 227 - qcom,kpss-acc-v2 228 - renesas,apmu 229 - renesas,r9a06g032-smp 230 - rockchip,rk3036-smp 231 - rockchip,rk3066-smp 232 - socionext,milbeaut-m10v-smp 233 - ste,dbx500-smp 234 235 cpu-release-addr: 236 $ref: '/schemas/types.yaml#/definitions/uint64' 237 238 description: 239 Required for systems that have an "enable-method" 240 property value of "spin-table". 241 On ARM v8 64-bit systems must be a two cell 242 property identifying a 64-bit zero-initialised 243 memory location. 244 245 cpu-idle-states: 246 $ref: '/schemas/types.yaml#/definitions/phandle-array' 247 description: | 248 List of phandles to idle state nodes supported 249 by this cpu (see ./idle-states.txt). 250 251 capacity-dmips-mhz: 252 $ref: '/schemas/types.yaml#/definitions/uint32' 253 description: 254 u32 value representing CPU capacity (see ./cpu-capacity.txt) in 255 DMIPS/MHz, relative to highest capacity-dmips-mhz 256 in the system. 257 258 dynamic-power-coefficient: 259 $ref: '/schemas/types.yaml#/definitions/uint32' 260 description: 261 A u32 value that represents the running time dynamic 262 power coefficient in units of uW/MHz/V^2. The 263 coefficient can either be calculated from power 264 measurements or derived by analysis. 265 266 The dynamic power consumption of the CPU is 267 proportional to the square of the Voltage (V) and 268 the clock frequency (f). The coefficient is used to 269 calculate the dynamic power as below - 270 271 Pdyn = dynamic-power-coefficient * V^2 * f 272 273 where voltage is in V, frequency is in MHz. 274 275 qcom,saw: 276 $ref: '/schemas/types.yaml#/definitions/phandle' 277 description: | 278 Specifies the SAW* node associated with this CPU. 279 280 Required for systems that have an "enable-method" property 281 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 282 283 * arm/msm/qcom,saw2.txt 284 285 qcom,acc: 286 $ref: '/schemas/types.yaml#/definitions/phandle' 287 description: | 288 Specifies the ACC* node associated with this CPU. 289 290 Required for systems that have an "enable-method" property 291 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 292 293 * arm/msm/qcom,kpss-acc.txt 294 295 rockchip,pmu: 296 $ref: '/schemas/types.yaml#/definitions/phandle' 297 description: | 298 Specifies the syscon node controlling the cpu core power domains. 299 300 Optional for systems that have an "enable-method" 301 property value of "rockchip,rk3066-smp" 302 While optional, it is the preferred way to get access to 303 the cpu-core power-domains. 304 305 required: 306 - device_type 307 - reg 308 - compatible 309 310 dependencies: 311 cpu-release-addr: [enable-method] 312 rockchip,pmu: [enable-method] 313 314required: 315 - '#address-cells' 316 - '#size-cells' 317 318examples: 319 - | 320 cpus { 321 #size-cells = <0>; 322 #address-cells = <1>; 323 324 cpu@0 { 325 device_type = "cpu"; 326 compatible = "arm,cortex-a15"; 327 reg = <0x0>; 328 }; 329 330 cpu@1 { 331 device_type = "cpu"; 332 compatible = "arm,cortex-a15"; 333 reg = <0x1>; 334 }; 335 336 cpu@100 { 337 device_type = "cpu"; 338 compatible = "arm,cortex-a7"; 339 reg = <0x100>; 340 }; 341 342 cpu@101 { 343 device_type = "cpu"; 344 compatible = "arm,cortex-a7"; 345 reg = <0x101>; 346 }; 347 }; 348 349 - | 350 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 351 cpus { 352 #size-cells = <0>; 353 #address-cells = <1>; 354 355 cpu@0 { 356 device_type = "cpu"; 357 compatible = "arm,cortex-a8"; 358 reg = <0x0>; 359 }; 360 }; 361 362 - | 363 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 364 cpus { 365 #size-cells = <0>; 366 #address-cells = <1>; 367 368 cpu@0 { 369 device_type = "cpu"; 370 compatible = "arm,arm926ej-s"; 371 reg = <0x0>; 372 }; 373 }; 374 375 - | 376 // Example 4 (ARM Cortex-A57 64-bit system): 377 cpus { 378 #size-cells = <0>; 379 #address-cells = <2>; 380 381 cpu@0 { 382 device_type = "cpu"; 383 compatible = "arm,cortex-a57"; 384 reg = <0x0 0x0>; 385 enable-method = "spin-table"; 386 cpu-release-addr = <0 0x20000000>; 387 }; 388 389 cpu@1 { 390 device_type = "cpu"; 391 compatible = "arm,cortex-a57"; 392 reg = <0x0 0x1>; 393 enable-method = "spin-table"; 394 cpu-release-addr = <0 0x20000000>; 395 }; 396 397 cpu@100 { 398 device_type = "cpu"; 399 compatible = "arm,cortex-a57"; 400 reg = <0x0 0x100>; 401 enable-method = "spin-table"; 402 cpu-release-addr = <0 0x20000000>; 403 }; 404 405 cpu@101 { 406 device_type = "cpu"; 407 compatible = "arm,cortex-a57"; 408 reg = <0x0 0x101>; 409 enable-method = "spin-table"; 410 cpu-release-addr = <0 0x20000000>; 411 }; 412 413 cpu@10000 { 414 device_type = "cpu"; 415 compatible = "arm,cortex-a57"; 416 reg = <0x0 0x10000>; 417 enable-method = "spin-table"; 418 cpu-release-addr = <0 0x20000000>; 419 }; 420 421 cpu@10001 { 422 device_type = "cpu"; 423 compatible = "arm,cortex-a57"; 424 reg = <0x0 0x10001>; 425 enable-method = "spin-table"; 426 cpu-release-addr = <0 0x20000000>; 427 }; 428 429 cpu@10100 { 430 device_type = "cpu"; 431 compatible = "arm,cortex-a57"; 432 reg = <0x0 0x10100>; 433 enable-method = "spin-table"; 434 cpu-release-addr = <0 0x20000000>; 435 }; 436 437 cpu@10101 { 438 device_type = "cpu"; 439 compatible = "arm,cortex-a57"; 440 reg = <0x0 0x10101>; 441 enable-method = "spin-table"; 442 cpu-release-addr = <0 0x20000000>; 443 }; 444 445 cpu@100000000 { 446 device_type = "cpu"; 447 compatible = "arm,cortex-a57"; 448 reg = <0x1 0x0>; 449 enable-method = "spin-table"; 450 cpu-release-addr = <0 0x20000000>; 451 }; 452 453 cpu@100000001 { 454 device_type = "cpu"; 455 compatible = "arm,cortex-a57"; 456 reg = <0x1 0x1>; 457 enable-method = "spin-table"; 458 cpu-release-addr = <0 0x20000000>; 459 }; 460 461 cpu@100000100 { 462 device_type = "cpu"; 463 compatible = "arm,cortex-a57"; 464 reg = <0x1 0x100>; 465 enable-method = "spin-table"; 466 cpu-release-addr = <0 0x20000000>; 467 }; 468 469 cpu@100000101 { 470 device_type = "cpu"; 471 compatible = "arm,cortex-a57"; 472 reg = <0x1 0x101>; 473 enable-method = "spin-table"; 474 cpu-release-addr = <0 0x20000000>; 475 }; 476 477 cpu@100010000 { 478 device_type = "cpu"; 479 compatible = "arm,cortex-a57"; 480 reg = <0x1 0x10000>; 481 enable-method = "spin-table"; 482 cpu-release-addr = <0 0x20000000>; 483 }; 484 485 cpu@100010001 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a57"; 488 reg = <0x1 0x10001>; 489 enable-method = "spin-table"; 490 cpu-release-addr = <0 0x20000000>; 491 }; 492 493 cpu@100010100 { 494 device_type = "cpu"; 495 compatible = "arm,cortex-a57"; 496 reg = <0x1 0x10100>; 497 enable-method = "spin-table"; 498 cpu-release-addr = <0 0x20000000>; 499 }; 500 501 cpu@100010101 { 502 device_type = "cpu"; 503 compatible = "arm,cortex-a57"; 504 reg = <0x1 0x10101>; 505 enable-method = "spin-table"; 506 cpu-release-addr = <0 0x20000000>; 507 }; 508 }; 509... 510