1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a53
127      - arm,cortex-a55
128      - arm,cortex-a57
129      - arm,cortex-a72
130      - arm,cortex-a73
131      - arm,cortex-m0
132      - arm,cortex-m0+
133      - arm,cortex-m1
134      - arm,cortex-m3
135      - arm,cortex-m4
136      - arm,cortex-r4
137      - arm,cortex-r5
138      - arm,cortex-r7
139      - brcm,brahma-b15
140      - brcm,brahma-b53
141      - brcm,vulcan
142      - cavium,thunder
143      - cavium,thunder2
144      - faraday,fa526
145      - intel,sa110
146      - intel,sa1100
147      - marvell,feroceon
148      - marvell,mohawk
149      - marvell,pj4a
150      - marvell,pj4b
151      - marvell,sheeva-v5
152      - marvell,sheeva-v7
153      - nvidia,tegra132-denver
154      - nvidia,tegra186-denver
155      - nvidia,tegra194-carmel
156      - qcom,krait
157      - qcom,kryo
158      - qcom,kryo385
159      - qcom,kryo485
160      - qcom,scorpion
161
162  enable-method:
163    allOf:
164      - $ref: '/schemas/types.yaml#/definitions/string'
165      - oneOf:
166          # On ARM v8 64-bit this property is required
167          - enum:
168              - psci
169              - spin-table
170          # On ARM 32-bit systems this property is optional
171          - enum:
172              - actions,s500-smp
173              - allwinner,sun6i-a31
174              - allwinner,sun8i-a23
175              - allwinner,sun9i-a80-smp
176              - allwinner,sun8i-a83t-smp
177              - amlogic,meson8-smp
178              - amlogic,meson8b-smp
179              - arm,realview-smp
180              - aspeed,ast2600-smp
181              - brcm,bcm11351-cpu-method
182              - brcm,bcm23550
183              - brcm,bcm2836-smp
184              - brcm,bcm63138
185              - brcm,bcm-nsp-smp
186              - brcm,brahma-b15
187              - marvell,armada-375-smp
188              - marvell,armada-380-smp
189              - marvell,armada-390-smp
190              - marvell,armada-xp-smp
191              - marvell,98dx3236-smp
192              - mediatek,mt6589-smp
193              - mediatek,mt81xx-tz-smp
194              - qcom,gcc-msm8660
195              - qcom,kpss-acc-v1
196              - qcom,kpss-acc-v2
197              - renesas,apmu
198              - renesas,r9a06g032-smp
199              - rockchip,rk3036-smp
200              - rockchip,rk3066-smp
201              - socionext,milbeaut-m10v-smp
202              - ste,dbx500-smp
203
204  cpu-release-addr:
205    $ref: '/schemas/types.yaml#/definitions/uint64'
206
207    description:
208      Required for systems that have an "enable-method"
209        property value of "spin-table".
210      On ARM v8 64-bit systems must be a two cell
211        property identifying a 64-bit zero-initialised
212        memory location.
213
214  cpu-idle-states:
215    $ref: '/schemas/types.yaml#/definitions/phandle-array'
216    description: |
217      List of phandles to idle state nodes supported
218      by this cpu (see ./idle-states.txt).
219
220  capacity-dmips-mhz:
221    $ref: '/schemas/types.yaml#/definitions/uint32'
222    description:
223      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
224      DMIPS/MHz, relative to highest capacity-dmips-mhz
225      in the system.
226
227  dynamic-power-coefficient:
228    $ref: '/schemas/types.yaml#/definitions/uint32'
229    description:
230      A u32 value that represents the running time dynamic
231      power coefficient in units of uW/MHz/V^2. The
232      coefficient can either be calculated from power
233      measurements or derived by analysis.
234
235      The dynamic power consumption of the CPU  is
236      proportional to the square of the Voltage (V) and
237      the clock frequency (f). The coefficient is used to
238      calculate the dynamic power as below -
239
240      Pdyn = dynamic-power-coefficient * V^2 * f
241
242      where voltage is in V, frequency is in MHz.
243
244  qcom,saw:
245    $ref: '/schemas/types.yaml#/definitions/phandle'
246    description: |
247      Specifies the SAW* node associated with this CPU.
248
249      Required for systems that have an "enable-method" property
250      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
251
252      * arm/msm/qcom,saw2.txt
253
254  qcom,acc:
255    $ref: '/schemas/types.yaml#/definitions/phandle'
256    description: |
257      Specifies the ACC* node associated with this CPU.
258
259      Required for systems that have an "enable-method" property
260      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
261
262      * arm/msm/qcom,kpss-acc.txt
263
264  rockchip,pmu:
265    $ref: '/schemas/types.yaml#/definitions/phandle'
266    description: |
267      Specifies the syscon node controlling the cpu core power domains.
268
269      Optional for systems that have an "enable-method"
270      property value of "rockchip,rk3066-smp"
271      While optional, it is the preferred way to get access to
272      the cpu-core power-domains.
273
274required:
275  - device_type
276  - reg
277  - compatible
278
279dependencies:
280  rockchip,pmu: [enable-method]
281
282examples:
283  - |
284    cpus {
285      #size-cells = <0>;
286      #address-cells = <1>;
287
288      cpu@0 {
289        device_type = "cpu";
290        compatible = "arm,cortex-a15";
291        reg = <0x0>;
292      };
293
294      cpu@1 {
295        device_type = "cpu";
296        compatible = "arm,cortex-a15";
297        reg = <0x1>;
298      };
299
300      cpu@100 {
301        device_type = "cpu";
302        compatible = "arm,cortex-a7";
303        reg = <0x100>;
304      };
305
306      cpu@101 {
307        device_type = "cpu";
308        compatible = "arm,cortex-a7";
309        reg = <0x101>;
310      };
311    };
312
313  - |
314    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
315    cpus {
316      #size-cells = <0>;
317      #address-cells = <1>;
318
319      cpu@0 {
320        device_type = "cpu";
321        compatible = "arm,cortex-a8";
322        reg = <0x0>;
323      };
324    };
325
326  - |
327    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
328    cpus {
329      #size-cells = <0>;
330      #address-cells = <1>;
331
332      cpu@0 {
333        device_type = "cpu";
334        compatible = "arm,arm926ej-s";
335        reg = <0x0>;
336      };
337    };
338
339  - |
340    //  Example 4 (ARM Cortex-A57 64-bit system):
341    cpus {
342      #size-cells = <0>;
343      #address-cells = <2>;
344
345      cpu@0 {
346        device_type = "cpu";
347        compatible = "arm,cortex-a57";
348        reg = <0x0 0x0>;
349        enable-method = "spin-table";
350        cpu-release-addr = <0 0x20000000>;
351      };
352
353      cpu@1 {
354        device_type = "cpu";
355        compatible = "arm,cortex-a57";
356        reg = <0x0 0x1>;
357        enable-method = "spin-table";
358        cpu-release-addr = <0 0x20000000>;
359      };
360
361      cpu@100 {
362        device_type = "cpu";
363        compatible = "arm,cortex-a57";
364        reg = <0x0 0x100>;
365        enable-method = "spin-table";
366        cpu-release-addr = <0 0x20000000>;
367      };
368
369      cpu@101 {
370        device_type = "cpu";
371        compatible = "arm,cortex-a57";
372        reg = <0x0 0x101>;
373        enable-method = "spin-table";
374        cpu-release-addr = <0 0x20000000>;
375      };
376
377      cpu@10000 {
378        device_type = "cpu";
379        compatible = "arm,cortex-a57";
380        reg = <0x0 0x10000>;
381        enable-method = "spin-table";
382        cpu-release-addr = <0 0x20000000>;
383      };
384
385      cpu@10001 {
386        device_type = "cpu";
387        compatible = "arm,cortex-a57";
388        reg = <0x0 0x10001>;
389        enable-method = "spin-table";
390        cpu-release-addr = <0 0x20000000>;
391      };
392
393      cpu@10100 {
394        device_type = "cpu";
395        compatible = "arm,cortex-a57";
396        reg = <0x0 0x10100>;
397        enable-method = "spin-table";
398        cpu-release-addr = <0 0x20000000>;
399      };
400
401      cpu@10101 {
402        device_type = "cpu";
403        compatible = "arm,cortex-a57";
404        reg = <0x0 0x10101>;
405        enable-method = "spin-table";
406        cpu-release-addr = <0 0x20000000>;
407      };
408
409      cpu@100000000 {
410        device_type = "cpu";
411        compatible = "arm,cortex-a57";
412        reg = <0x1 0x0>;
413        enable-method = "spin-table";
414        cpu-release-addr = <0 0x20000000>;
415      };
416
417      cpu@100000001 {
418        device_type = "cpu";
419        compatible = "arm,cortex-a57";
420        reg = <0x1 0x1>;
421        enable-method = "spin-table";
422        cpu-release-addr = <0 0x20000000>;
423      };
424
425      cpu@100000100 {
426        device_type = "cpu";
427        compatible = "arm,cortex-a57";
428        reg = <0x1 0x100>;
429        enable-method = "spin-table";
430        cpu-release-addr = <0 0x20000000>;
431      };
432
433      cpu@100000101 {
434        device_type = "cpu";
435        compatible = "arm,cortex-a57";
436        reg = <0x1 0x101>;
437        enable-method = "spin-table";
438        cpu-release-addr = <0 0x20000000>;
439      };
440
441      cpu@100010000 {
442        device_type = "cpu";
443        compatible = "arm,cortex-a57";
444        reg = <0x1 0x10000>;
445        enable-method = "spin-table";
446        cpu-release-addr = <0 0x20000000>;
447      };
448
449      cpu@100010001 {
450        device_type = "cpu";
451        compatible = "arm,cortex-a57";
452        reg = <0x1 0x10001>;
453        enable-method = "spin-table";
454        cpu-release-addr = <0 0x20000000>;
455      };
456
457      cpu@100010100 {
458        device_type = "cpu";
459        compatible = "arm,cortex-a57";
460        reg = <0x1 0x10100>;
461        enable-method = "spin-table";
462        cpu-release-addr = <0 0x20000000>;
463      };
464
465      cpu@100010101 {
466        device_type = "cpu";
467        compatible = "arm,cortex-a57";
468        reg = <0x1 0x10101>;
469        enable-method = "spin-table";
470        cpu-release-addr = <0 0x20000000>;
471      };
472    };
473...
474