1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a78ae
142      - arm,cortex-a510
143      - arm,cortex-a710
144      - arm,cortex-a715
145      - arm,cortex-m0
146      - arm,cortex-m0+
147      - arm,cortex-m1
148      - arm,cortex-m3
149      - arm,cortex-m4
150      - arm,cortex-r4
151      - arm,cortex-r5
152      - arm,cortex-r7
153      - arm,cortex-x1
154      - arm,cortex-x2
155      - arm,cortex-x3
156      - arm,neoverse-e1
157      - arm,neoverse-n1
158      - arm,neoverse-n2
159      - arm,neoverse-v1
160      - brcm,brahma-b15
161      - brcm,brahma-b53
162      - brcm,vulcan
163      - cavium,thunder
164      - cavium,thunder2
165      - faraday,fa526
166      - intel,sa110
167      - intel,sa1100
168      - marvell,feroceon
169      - marvell,mohawk
170      - marvell,pj4a
171      - marvell,pj4b
172      - marvell,sheeva-v5
173      - marvell,sheeva-v7
174      - nvidia,tegra132-denver
175      - nvidia,tegra186-denver
176      - nvidia,tegra194-carmel
177      - qcom,krait
178      - qcom,kryo
179      - qcom,kryo240
180      - qcom,kryo250
181      - qcom,kryo260
182      - qcom,kryo280
183      - qcom,kryo360
184      - qcom,kryo385
185      - qcom,kryo468
186      - qcom,kryo485
187      - qcom,kryo560
188      - qcom,kryo570
189      - qcom,kryo660
190      - qcom,kryo685
191      - qcom,kryo780
192      - qcom,scorpion
193
194  enable-method:
195    $ref: '/schemas/types.yaml#/definitions/string'
196    oneOf:
197      # On ARM v8 64-bit this property is required
198      - enum:
199          - psci
200          - spin-table
201      # On ARM 32-bit systems this property is optional
202      - enum:
203          - actions,s500-smp
204          - allwinner,sun6i-a31
205          - allwinner,sun8i-a23
206          - allwinner,sun9i-a80-smp
207          - allwinner,sun8i-a83t-smp
208          - amlogic,meson8-smp
209          - amlogic,meson8b-smp
210          - arm,realview-smp
211          - aspeed,ast2600-smp
212          - brcm,bcm11351-cpu-method
213          - brcm,bcm23550
214          - brcm,bcm2836-smp
215          - brcm,bcm63138
216          - brcm,bcm-nsp-smp
217          - brcm,brahma-b15
218          - marvell,armada-375-smp
219          - marvell,armada-380-smp
220          - marvell,armada-390-smp
221          - marvell,armada-xp-smp
222          - marvell,98dx3236-smp
223          - marvell,mmp3-smp
224          - mediatek,mt6589-smp
225          - mediatek,mt81xx-tz-smp
226          - qcom,gcc-msm8660
227          - qcom,kpss-acc-v1
228          - qcom,kpss-acc-v2
229          - qcom,msm8226-smp
230          - qcom,msm8909-smp
231          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
232          - qcom,msm8916-smp
233          - renesas,apmu
234          - renesas,r9a06g032-smp
235          - rockchip,rk3036-smp
236          - rockchip,rk3066-smp
237          - socionext,milbeaut-m10v-smp
238          - ste,dbx500-smp
239          - ti,am3352
240          - ti,am4372
241
242  cpu-release-addr:
243    oneOf:
244      - $ref: '/schemas/types.yaml#/definitions/uint32'
245      - $ref: '/schemas/types.yaml#/definitions/uint64'
246    description:
247      The DT specification defines this as 64-bit always, but some 32-bit Arm
248      systems have used a 32-bit value which must be supported.
249      Required for systems that have an "enable-method"
250        property value of "spin-table".
251
252  cpu-idle-states:
253    $ref: '/schemas/types.yaml#/definitions/phandle-array'
254    items:
255      maxItems: 1
256    description: |
257      List of phandles to idle state nodes supported
258      by this cpu (see ./idle-states.yaml).
259
260  capacity-dmips-mhz:
261    description:
262      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
263      DMIPS/MHz, relative to highest capacity-dmips-mhz
264      in the system.
265
266  cci-control-port: true
267
268  dynamic-power-coefficient:
269    $ref: '/schemas/types.yaml#/definitions/uint32'
270    description:
271      A u32 value that represents the running time dynamic
272      power coefficient in units of uW/MHz/V^2. The
273      coefficient can either be calculated from power
274      measurements or derived by analysis.
275
276      The dynamic power consumption of the CPU  is
277      proportional to the square of the Voltage (V) and
278      the clock frequency (f). The coefficient is used to
279      calculate the dynamic power as below -
280
281      Pdyn = dynamic-power-coefficient * V^2 * f
282
283      where voltage is in V, frequency is in MHz.
284
285  performance-domains:
286    maxItems: 1
287    description:
288      List of phandles and performance domain specifiers, as defined by
289      bindings of the performance domain provider. See also
290      dvfs/performance-domain.yaml.
291
292  power-domains:
293    description:
294      List of phandles and PM domain specifiers, as defined by bindings of the
295      PM domain provider (see also ../power_domain.txt).
296
297  power-domain-names:
298    description:
299      A list of power domain name strings sorted in the same order as the
300      power-domains property.
301
302      For PSCI based platforms, the name corresponding to the index of the PSCI
303      PM domain provider, must be "psci".
304
305  qcom,saw:
306    $ref: '/schemas/types.yaml#/definitions/phandle'
307    description: |
308      Specifies the SAW* node associated with this CPU.
309
310      Required for systems that have an "enable-method" property
311      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
312
313      * arm/msm/qcom,saw2.txt
314
315  qcom,acc:
316    $ref: '/schemas/types.yaml#/definitions/phandle'
317    description: |
318      Specifies the ACC* node associated with this CPU.
319
320      Required for systems that have an "enable-method" property
321      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
322      "qcom,msm8916-smp".
323
324      * arm/msm/qcom,kpss-acc.txt
325
326  rockchip,pmu:
327    $ref: '/schemas/types.yaml#/definitions/phandle'
328    description: |
329      Specifies the syscon node controlling the cpu core power domains.
330
331      Optional for systems that have an "enable-method"
332      property value of "rockchip,rk3066-smp"
333      While optional, it is the preferred way to get access to
334      the cpu-core power-domains.
335
336  secondary-boot-reg:
337    $ref: '/schemas/types.yaml#/definitions/uint32'
338    description: |
339      Required for systems that have an "enable-method" property value of
340      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
341
342      This includes the following SoCs: |
343      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
344      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
345
346      The secondary-boot-reg property is a u32 value that specifies the
347      physical address of the register used to request the ROM holding pen
348      code release a secondary CPU. The value written to the register is
349      formed by encoding the target CPU id into the low bits of the
350      physical start address it should jump to.
351
352if:
353  # If the enable-method property contains one of those values
354  properties:
355    enable-method:
356      contains:
357        enum:
358          - brcm,bcm11351-cpu-method
359          - brcm,bcm23550
360          - brcm,bcm-nsp-smp
361  # and if enable-method is present
362  required:
363    - enable-method
364
365then:
366  required:
367    - secondary-boot-reg
368
369required:
370  - device_type
371  - reg
372  - compatible
373
374dependencies:
375  rockchip,pmu: [enable-method]
376
377additionalProperties: true
378
379examples:
380  - |
381    cpus {
382      #size-cells = <0>;
383      #address-cells = <1>;
384
385      cpu@0 {
386        device_type = "cpu";
387        compatible = "arm,cortex-a15";
388        reg = <0x0>;
389      };
390
391      cpu@1 {
392        device_type = "cpu";
393        compatible = "arm,cortex-a15";
394        reg = <0x1>;
395      };
396
397      cpu@100 {
398        device_type = "cpu";
399        compatible = "arm,cortex-a7";
400        reg = <0x100>;
401      };
402
403      cpu@101 {
404        device_type = "cpu";
405        compatible = "arm,cortex-a7";
406        reg = <0x101>;
407      };
408    };
409
410  - |
411    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
412    cpus {
413      #size-cells = <0>;
414      #address-cells = <1>;
415
416      cpu@0 {
417        device_type = "cpu";
418        compatible = "arm,cortex-a8";
419        reg = <0x0>;
420      };
421    };
422
423  - |
424    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
425    cpus {
426      #size-cells = <0>;
427      #address-cells = <1>;
428
429      cpu@0 {
430        device_type = "cpu";
431        compatible = "arm,arm926ej-s";
432        reg = <0x0>;
433      };
434    };
435
436  - |
437    //  Example 4 (ARM Cortex-A57 64-bit system):
438    cpus {
439      #size-cells = <0>;
440      #address-cells = <2>;
441
442      cpu@0 {
443        device_type = "cpu";
444        compatible = "arm,cortex-a57";
445        reg = <0x0 0x0>;
446        enable-method = "spin-table";
447        cpu-release-addr = <0 0x20000000>;
448      };
449
450      cpu@1 {
451        device_type = "cpu";
452        compatible = "arm,cortex-a57";
453        reg = <0x0 0x1>;
454        enable-method = "spin-table";
455        cpu-release-addr = <0 0x20000000>;
456      };
457
458      cpu@100 {
459        device_type = "cpu";
460        compatible = "arm,cortex-a57";
461        reg = <0x0 0x100>;
462        enable-method = "spin-table";
463        cpu-release-addr = <0 0x20000000>;
464      };
465
466      cpu@101 {
467        device_type = "cpu";
468        compatible = "arm,cortex-a57";
469        reg = <0x0 0x101>;
470        enable-method = "spin-table";
471        cpu-release-addr = <0 0x20000000>;
472      };
473
474      cpu@10000 {
475        device_type = "cpu";
476        compatible = "arm,cortex-a57";
477        reg = <0x0 0x10000>;
478        enable-method = "spin-table";
479        cpu-release-addr = <0 0x20000000>;
480      };
481
482      cpu@10001 {
483        device_type = "cpu";
484        compatible = "arm,cortex-a57";
485        reg = <0x0 0x10001>;
486        enable-method = "spin-table";
487        cpu-release-addr = <0 0x20000000>;
488      };
489
490      cpu@10100 {
491        device_type = "cpu";
492        compatible = "arm,cortex-a57";
493        reg = <0x0 0x10100>;
494        enable-method = "spin-table";
495        cpu-release-addr = <0 0x20000000>;
496      };
497
498      cpu@10101 {
499        device_type = "cpu";
500        compatible = "arm,cortex-a57";
501        reg = <0x0 0x10101>;
502        enable-method = "spin-table";
503        cpu-release-addr = <0 0x20000000>;
504      };
505
506      cpu@100000000 {
507        device_type = "cpu";
508        compatible = "arm,cortex-a57";
509        reg = <0x1 0x0>;
510        enable-method = "spin-table";
511        cpu-release-addr = <0 0x20000000>;
512      };
513
514      cpu@100000001 {
515        device_type = "cpu";
516        compatible = "arm,cortex-a57";
517        reg = <0x1 0x1>;
518        enable-method = "spin-table";
519        cpu-release-addr = <0 0x20000000>;
520      };
521
522      cpu@100000100 {
523        device_type = "cpu";
524        compatible = "arm,cortex-a57";
525        reg = <0x1 0x100>;
526        enable-method = "spin-table";
527        cpu-release-addr = <0 0x20000000>;
528      };
529
530      cpu@100000101 {
531        device_type = "cpu";
532        compatible = "arm,cortex-a57";
533        reg = <0x1 0x101>;
534        enable-method = "spin-table";
535        cpu-release-addr = <0 0x20000000>;
536      };
537
538      cpu@100010000 {
539        device_type = "cpu";
540        compatible = "arm,cortex-a57";
541        reg = <0x1 0x10000>;
542        enable-method = "spin-table";
543        cpu-release-addr = <0 0x20000000>;
544      };
545
546      cpu@100010001 {
547        device_type = "cpu";
548        compatible = "arm,cortex-a57";
549        reg = <0x1 0x10001>;
550        enable-method = "spin-table";
551        cpu-release-addr = <0 0x20000000>;
552      };
553
554      cpu@100010100 {
555        device_type = "cpu";
556        compatible = "arm,cortex-a57";
557        reg = <0x1 0x10100>;
558        enable-method = "spin-table";
559        cpu-release-addr = <0 0x20000000>;
560      };
561
562      cpu@100010101 {
563        device_type = "cpu";
564        compatible = "arm,cortex-a57";
565        reg = <0x1 0x10101>;
566        enable-method = "spin-table";
567        cpu-release-addr = <0 0x20000000>;
568      };
569    };
570...
571