1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,avalanche
89      - apple,blizzard
90      - apple,icestorm
91      - apple,firestorm
92      - arm,arm710t
93      - arm,arm720t
94      - arm,arm740t
95      - arm,arm7ej-s
96      - arm,arm7tdmi
97      - arm,arm7tdmi-s
98      - arm,arm9es
99      - arm,arm9ej-s
100      - arm,arm920t
101      - arm,arm922t
102      - arm,arm925
103      - arm,arm926e-s
104      - arm,arm926ej-s
105      - arm,arm940t
106      - arm,arm946e-s
107      - arm,arm966e-s
108      - arm,arm968e-s
109      - arm,arm9tdmi
110      - arm,arm1020e
111      - arm,arm1020t
112      - arm,arm1022e
113      - arm,arm1026ej-s
114      - arm,arm1136j-s
115      - arm,arm1136jf-s
116      - arm,arm1156t2-s
117      - arm,arm1156t2f-s
118      - arm,arm1176jzf
119      - arm,arm1176jz-s
120      - arm,arm1176jzf-s
121      - arm,arm11mpcore
122      - arm,armv8 # Only for s/w models
123      - arm,cortex-a5
124      - arm,cortex-a7
125      - arm,cortex-a8
126      - arm,cortex-a9
127      - arm,cortex-a12
128      - arm,cortex-a15
129      - arm,cortex-a17
130      - arm,cortex-a32
131      - arm,cortex-a34
132      - arm,cortex-a35
133      - arm,cortex-a53
134      - arm,cortex-a55
135      - arm,cortex-a57
136      - arm,cortex-a65
137      - arm,cortex-a72
138      - arm,cortex-a73
139      - arm,cortex-a75
140      - arm,cortex-a76
141      - arm,cortex-a77
142      - arm,cortex-a78
143      - arm,cortex-a78ae
144      - arm,cortex-a510
145      - arm,cortex-a710
146      - arm,cortex-a715
147      - arm,cortex-m0
148      - arm,cortex-m0+
149      - arm,cortex-m1
150      - arm,cortex-m3
151      - arm,cortex-m4
152      - arm,cortex-r4
153      - arm,cortex-r5
154      - arm,cortex-r7
155      - arm,cortex-x1
156      - arm,cortex-x2
157      - arm,cortex-x3
158      - arm,neoverse-e1
159      - arm,neoverse-n1
160      - arm,neoverse-n2
161      - arm,neoverse-v1
162      - brcm,brahma-b15
163      - brcm,brahma-b53
164      - brcm,vulcan
165      - cavium,thunder
166      - cavium,thunder2
167      - faraday,fa526
168      - intel,sa110
169      - intel,sa1100
170      - marvell,feroceon
171      - marvell,mohawk
172      - marvell,pj4a
173      - marvell,pj4b
174      - marvell,sheeva-v5
175      - marvell,sheeva-v7
176      - nvidia,tegra132-denver
177      - nvidia,tegra186-denver
178      - nvidia,tegra194-carmel
179      - qcom,krait
180      - qcom,kryo
181      - qcom,kryo240
182      - qcom,kryo250
183      - qcom,kryo260
184      - qcom,kryo280
185      - qcom,kryo360
186      - qcom,kryo385
187      - qcom,kryo468
188      - qcom,kryo485
189      - qcom,kryo560
190      - qcom,kryo570
191      - qcom,kryo660
192      - qcom,kryo685
193      - qcom,kryo780
194      - qcom,scorpion
195
196  enable-method:
197    $ref: '/schemas/types.yaml#/definitions/string'
198    oneOf:
199      # On ARM v8 64-bit this property is required
200      - enum:
201          - psci
202          - spin-table
203      # On ARM 32-bit systems this property is optional
204      - enum:
205          - actions,s500-smp
206          - allwinner,sun6i-a31
207          - allwinner,sun8i-a23
208          - allwinner,sun9i-a80-smp
209          - allwinner,sun8i-a83t-smp
210          - amlogic,meson8-smp
211          - amlogic,meson8b-smp
212          - arm,realview-smp
213          - aspeed,ast2600-smp
214          - brcm,bcm11351-cpu-method
215          - brcm,bcm23550
216          - brcm,bcm2836-smp
217          - brcm,bcm63138
218          - brcm,bcm-nsp-smp
219          - brcm,brahma-b15
220          - marvell,armada-375-smp
221          - marvell,armada-380-smp
222          - marvell,armada-390-smp
223          - marvell,armada-xp-smp
224          - marvell,98dx3236-smp
225          - marvell,mmp3-smp
226          - mediatek,mt6589-smp
227          - mediatek,mt81xx-tz-smp
228          - qcom,gcc-msm8660
229          - qcom,kpss-acc-v1
230          - qcom,kpss-acc-v2
231          - qcom,msm8226-smp
232          - qcom,msm8909-smp
233          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
234          - qcom,msm8916-smp
235          - renesas,apmu
236          - renesas,r9a06g032-smp
237          - rockchip,rk3036-smp
238          - rockchip,rk3066-smp
239          - socionext,milbeaut-m10v-smp
240          - ste,dbx500-smp
241          - ti,am3352
242          - ti,am4372
243
244  cpu-release-addr:
245    oneOf:
246      - $ref: '/schemas/types.yaml#/definitions/uint32'
247      - $ref: '/schemas/types.yaml#/definitions/uint64'
248    description:
249      The DT specification defines this as 64-bit always, but some 32-bit Arm
250      systems have used a 32-bit value which must be supported.
251      Required for systems that have an "enable-method"
252        property value of "spin-table".
253
254  cpu-idle-states:
255    $ref: '/schemas/types.yaml#/definitions/phandle-array'
256    items:
257      maxItems: 1
258    description: |
259      List of phandles to idle state nodes supported
260      by this cpu (see ./idle-states.yaml).
261
262  capacity-dmips-mhz:
263    description:
264      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
265      DMIPS/MHz, relative to highest capacity-dmips-mhz
266      in the system.
267
268  cci-control-port: true
269
270  dynamic-power-coefficient:
271    $ref: '/schemas/types.yaml#/definitions/uint32'
272    description:
273      A u32 value that represents the running time dynamic
274      power coefficient in units of uW/MHz/V^2. The
275      coefficient can either be calculated from power
276      measurements or derived by analysis.
277
278      The dynamic power consumption of the CPU  is
279      proportional to the square of the Voltage (V) and
280      the clock frequency (f). The coefficient is used to
281      calculate the dynamic power as below -
282
283      Pdyn = dynamic-power-coefficient * V^2 * f
284
285      where voltage is in V, frequency is in MHz.
286
287  performance-domains:
288    maxItems: 1
289    description:
290      List of phandles and performance domain specifiers, as defined by
291      bindings of the performance domain provider. See also
292      dvfs/performance-domain.yaml.
293
294  power-domains:
295    description:
296      List of phandles and PM domain specifiers, as defined by bindings of the
297      PM domain provider (see also ../power_domain.txt).
298
299  power-domain-names:
300    description:
301      A list of power domain name strings sorted in the same order as the
302      power-domains property.
303
304      For PSCI based platforms, the name corresponding to the index of the PSCI
305      PM domain provider, must be "psci".
306
307  qcom,saw:
308    $ref: '/schemas/types.yaml#/definitions/phandle'
309    description: |
310      Specifies the SAW* node associated with this CPU.
311
312      Required for systems that have an "enable-method" property
313      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
314
315      * arm/msm/qcom,saw2.txt
316
317  qcom,acc:
318    $ref: '/schemas/types.yaml#/definitions/phandle'
319    description: |
320      Specifies the ACC* node associated with this CPU.
321
322      Required for systems that have an "enable-method" property
323      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
324      "qcom,msm8916-smp".
325
326      * arm/msm/qcom,kpss-acc.txt
327
328  rockchip,pmu:
329    $ref: '/schemas/types.yaml#/definitions/phandle'
330    description: |
331      Specifies the syscon node controlling the cpu core power domains.
332
333      Optional for systems that have an "enable-method"
334      property value of "rockchip,rk3066-smp"
335      While optional, it is the preferred way to get access to
336      the cpu-core power-domains.
337
338  secondary-boot-reg:
339    $ref: '/schemas/types.yaml#/definitions/uint32'
340    description: |
341      Required for systems that have an "enable-method" property value of
342      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
343
344      This includes the following SoCs: |
345      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
346      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
347
348      The secondary-boot-reg property is a u32 value that specifies the
349      physical address of the register used to request the ROM holding pen
350      code release a secondary CPU. The value written to the register is
351      formed by encoding the target CPU id into the low bits of the
352      physical start address it should jump to.
353
354if:
355  # If the enable-method property contains one of those values
356  properties:
357    enable-method:
358      contains:
359        enum:
360          - brcm,bcm11351-cpu-method
361          - brcm,bcm23550
362          - brcm,bcm-nsp-smp
363  # and if enable-method is present
364  required:
365    - enable-method
366
367then:
368  required:
369    - secondary-boot-reg
370
371required:
372  - device_type
373  - reg
374  - compatible
375
376dependencies:
377  rockchip,pmu: [enable-method]
378
379additionalProperties: true
380
381examples:
382  - |
383    cpus {
384      #size-cells = <0>;
385      #address-cells = <1>;
386
387      cpu@0 {
388        device_type = "cpu";
389        compatible = "arm,cortex-a15";
390        reg = <0x0>;
391      };
392
393      cpu@1 {
394        device_type = "cpu";
395        compatible = "arm,cortex-a15";
396        reg = <0x1>;
397      };
398
399      cpu@100 {
400        device_type = "cpu";
401        compatible = "arm,cortex-a7";
402        reg = <0x100>;
403      };
404
405      cpu@101 {
406        device_type = "cpu";
407        compatible = "arm,cortex-a7";
408        reg = <0x101>;
409      };
410    };
411
412  - |
413    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
414    cpus {
415      #size-cells = <0>;
416      #address-cells = <1>;
417
418      cpu@0 {
419        device_type = "cpu";
420        compatible = "arm,cortex-a8";
421        reg = <0x0>;
422      };
423    };
424
425  - |
426    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
427    cpus {
428      #size-cells = <0>;
429      #address-cells = <1>;
430
431      cpu@0 {
432        device_type = "cpu";
433        compatible = "arm,arm926ej-s";
434        reg = <0x0>;
435      };
436    };
437
438  - |
439    //  Example 4 (ARM Cortex-A57 64-bit system):
440    cpus {
441      #size-cells = <0>;
442      #address-cells = <2>;
443
444      cpu@0 {
445        device_type = "cpu";
446        compatible = "arm,cortex-a57";
447        reg = <0x0 0x0>;
448        enable-method = "spin-table";
449        cpu-release-addr = <0 0x20000000>;
450      };
451
452      cpu@1 {
453        device_type = "cpu";
454        compatible = "arm,cortex-a57";
455        reg = <0x0 0x1>;
456        enable-method = "spin-table";
457        cpu-release-addr = <0 0x20000000>;
458      };
459
460      cpu@100 {
461        device_type = "cpu";
462        compatible = "arm,cortex-a57";
463        reg = <0x0 0x100>;
464        enable-method = "spin-table";
465        cpu-release-addr = <0 0x20000000>;
466      };
467
468      cpu@101 {
469        device_type = "cpu";
470        compatible = "arm,cortex-a57";
471        reg = <0x0 0x101>;
472        enable-method = "spin-table";
473        cpu-release-addr = <0 0x20000000>;
474      };
475
476      cpu@10000 {
477        device_type = "cpu";
478        compatible = "arm,cortex-a57";
479        reg = <0x0 0x10000>;
480        enable-method = "spin-table";
481        cpu-release-addr = <0 0x20000000>;
482      };
483
484      cpu@10001 {
485        device_type = "cpu";
486        compatible = "arm,cortex-a57";
487        reg = <0x0 0x10001>;
488        enable-method = "spin-table";
489        cpu-release-addr = <0 0x20000000>;
490      };
491
492      cpu@10100 {
493        device_type = "cpu";
494        compatible = "arm,cortex-a57";
495        reg = <0x0 0x10100>;
496        enable-method = "spin-table";
497        cpu-release-addr = <0 0x20000000>;
498      };
499
500      cpu@10101 {
501        device_type = "cpu";
502        compatible = "arm,cortex-a57";
503        reg = <0x0 0x10101>;
504        enable-method = "spin-table";
505        cpu-release-addr = <0 0x20000000>;
506      };
507
508      cpu@100000000 {
509        device_type = "cpu";
510        compatible = "arm,cortex-a57";
511        reg = <0x1 0x0>;
512        enable-method = "spin-table";
513        cpu-release-addr = <0 0x20000000>;
514      };
515
516      cpu@100000001 {
517        device_type = "cpu";
518        compatible = "arm,cortex-a57";
519        reg = <0x1 0x1>;
520        enable-method = "spin-table";
521        cpu-release-addr = <0 0x20000000>;
522      };
523
524      cpu@100000100 {
525        device_type = "cpu";
526        compatible = "arm,cortex-a57";
527        reg = <0x1 0x100>;
528        enable-method = "spin-table";
529        cpu-release-addr = <0 0x20000000>;
530      };
531
532      cpu@100000101 {
533        device_type = "cpu";
534        compatible = "arm,cortex-a57";
535        reg = <0x1 0x101>;
536        enable-method = "spin-table";
537        cpu-release-addr = <0 0x20000000>;
538      };
539
540      cpu@100010000 {
541        device_type = "cpu";
542        compatible = "arm,cortex-a57";
543        reg = <0x1 0x10000>;
544        enable-method = "spin-table";
545        cpu-release-addr = <0 0x20000000>;
546      };
547
548      cpu@100010001 {
549        device_type = "cpu";
550        compatible = "arm,cortex-a57";
551        reg = <0x1 0x10001>;
552        enable-method = "spin-table";
553        cpu-release-addr = <0 0x20000000>;
554      };
555
556      cpu@100010100 {
557        device_type = "cpu";
558        compatible = "arm,cortex-a57";
559        reg = <0x1 0x10100>;
560        enable-method = "spin-table";
561        cpu-release-addr = <0 0x20000000>;
562      };
563
564      cpu@100010101 {
565        device_type = "cpu";
566        compatible = "arm,cortex-a57";
567        reg = <0x1 0x10101>;
568        enable-method = "spin-table";
569        cpu-release-addr = <0 0x20000000>;
570      };
571    };
572...
573