1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a510
142      - arm,cortex-a710
143      - arm,cortex-m0
144      - arm,cortex-m0+
145      - arm,cortex-m1
146      - arm,cortex-m3
147      - arm,cortex-m4
148      - arm,cortex-r4
149      - arm,cortex-r5
150      - arm,cortex-r7
151      - arm,cortex-x1
152      - arm,cortex-x2
153      - arm,neoverse-e1
154      - arm,neoverse-n1
155      - arm,neoverse-n2
156      - arm,neoverse-v1
157      - brcm,brahma-b15
158      - brcm,brahma-b53
159      - brcm,vulcan
160      - cavium,thunder
161      - cavium,thunder2
162      - faraday,fa526
163      - intel,sa110
164      - intel,sa1100
165      - marvell,feroceon
166      - marvell,mohawk
167      - marvell,pj4a
168      - marvell,pj4b
169      - marvell,sheeva-v5
170      - marvell,sheeva-v7
171      - nvidia,tegra132-denver
172      - nvidia,tegra186-denver
173      - nvidia,tegra194-carmel
174      - qcom,krait
175      - qcom,kryo
176      - qcom,kryo260
177      - qcom,kryo280
178      - qcom,kryo385
179      - qcom,kryo468
180      - qcom,kryo485
181      - qcom,kryo560
182      - qcom,kryo570
183      - qcom,kryo685
184      - qcom,kryo780
185      - qcom,scorpion
186
187  enable-method:
188    $ref: '/schemas/types.yaml#/definitions/string'
189    oneOf:
190      # On ARM v8 64-bit this property is required
191      - enum:
192          - psci
193          - spin-table
194      # On ARM 32-bit systems this property is optional
195      - enum:
196          - actions,s500-smp
197          - allwinner,sun6i-a31
198          - allwinner,sun8i-a23
199          - allwinner,sun9i-a80-smp
200          - allwinner,sun8i-a83t-smp
201          - amlogic,meson8-smp
202          - amlogic,meson8b-smp
203          - arm,realview-smp
204          - aspeed,ast2600-smp
205          - brcm,bcm11351-cpu-method
206          - brcm,bcm23550
207          - brcm,bcm2836-smp
208          - brcm,bcm63138
209          - brcm,bcm-nsp-smp
210          - brcm,brahma-b15
211          - marvell,armada-375-smp
212          - marvell,armada-380-smp
213          - marvell,armada-390-smp
214          - marvell,armada-xp-smp
215          - marvell,98dx3236-smp
216          - marvell,mmp3-smp
217          - mediatek,mt6589-smp
218          - mediatek,mt81xx-tz-smp
219          - qcom,gcc-msm8660
220          - qcom,kpss-acc-v1
221          - qcom,kpss-acc-v2
222          - qcom,msm8226-smp
223          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
224          - qcom,msm8916-smp
225          - renesas,apmu
226          - renesas,r9a06g032-smp
227          - rockchip,rk3036-smp
228          - rockchip,rk3066-smp
229          - socionext,milbeaut-m10v-smp
230          - ste,dbx500-smp
231          - ti,am3352
232          - ti,am4372
233
234  cpu-release-addr:
235    $ref: '/schemas/types.yaml#/definitions/uint64'
236
237    description:
238      Required for systems that have an "enable-method"
239        property value of "spin-table".
240      On ARM v8 64-bit systems must be a two cell
241        property identifying a 64-bit zero-initialised
242        memory location.
243
244  cpu-idle-states:
245    $ref: '/schemas/types.yaml#/definitions/phandle-array'
246    description: |
247      List of phandles to idle state nodes supported
248      by this cpu (see ./idle-states.yaml).
249
250  capacity-dmips-mhz:
251    description:
252      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
253      DMIPS/MHz, relative to highest capacity-dmips-mhz
254      in the system.
255
256  cci-control-port: true
257
258  dynamic-power-coefficient:
259    $ref: '/schemas/types.yaml#/definitions/uint32'
260    description:
261      A u32 value that represents the running time dynamic
262      power coefficient in units of uW/MHz/V^2. The
263      coefficient can either be calculated from power
264      measurements or derived by analysis.
265
266      The dynamic power consumption of the CPU  is
267      proportional to the square of the Voltage (V) and
268      the clock frequency (f). The coefficient is used to
269      calculate the dynamic power as below -
270
271      Pdyn = dynamic-power-coefficient * V^2 * f
272
273      where voltage is in V, frequency is in MHz.
274
275  performance-domains:
276    maxItems: 1
277    description:
278      List of phandles and performance domain specifiers, as defined by
279      bindings of the performance domain provider. See also
280      dvfs/performance-domain.yaml.
281
282  power-domains:
283    description:
284      List of phandles and PM domain specifiers, as defined by bindings of the
285      PM domain provider (see also ../power_domain.txt).
286
287  power-domain-names:
288    description:
289      A list of power domain name strings sorted in the same order as the
290      power-domains property.
291
292      For PSCI based platforms, the name corresponding to the index of the PSCI
293      PM domain provider, must be "psci".
294
295  qcom,saw:
296    $ref: '/schemas/types.yaml#/definitions/phandle'
297    description: |
298      Specifies the SAW* node associated with this CPU.
299
300      Required for systems that have an "enable-method" property
301      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
302
303      * arm/msm/qcom,saw2.txt
304
305  qcom,acc:
306    $ref: '/schemas/types.yaml#/definitions/phandle'
307    description: |
308      Specifies the ACC* node associated with this CPU.
309
310      Required for systems that have an "enable-method" property
311      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
312      "qcom,msm8916-smp".
313
314      * arm/msm/qcom,kpss-acc.txt
315
316  rockchip,pmu:
317    $ref: '/schemas/types.yaml#/definitions/phandle'
318    description: |
319      Specifies the syscon node controlling the cpu core power domains.
320
321      Optional for systems that have an "enable-method"
322      property value of "rockchip,rk3066-smp"
323      While optional, it is the preferred way to get access to
324      the cpu-core power-domains.
325
326  secondary-boot-reg:
327    $ref: '/schemas/types.yaml#/definitions/uint32'
328    description: |
329      Required for systems that have an "enable-method" property value of
330      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
331
332      This includes the following SoCs: |
333      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
334      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
335
336      The secondary-boot-reg property is a u32 value that specifies the
337      physical address of the register used to request the ROM holding pen
338      code release a secondary CPU. The value written to the register is
339      formed by encoding the target CPU id into the low bits of the
340      physical start address it should jump to.
341
342if:
343  # If the enable-method property contains one of those values
344  properties:
345    enable-method:
346      contains:
347        enum:
348          - brcm,bcm11351-cpu-method
349          - brcm,bcm23550
350          - brcm,bcm-nsp-smp
351  # and if enable-method is present
352  required:
353    - enable-method
354
355then:
356  required:
357    - secondary-boot-reg
358
359required:
360  - device_type
361  - reg
362  - compatible
363
364dependencies:
365  rockchip,pmu: [enable-method]
366
367additionalProperties: true
368
369examples:
370  - |
371    cpus {
372      #size-cells = <0>;
373      #address-cells = <1>;
374
375      cpu@0 {
376        device_type = "cpu";
377        compatible = "arm,cortex-a15";
378        reg = <0x0>;
379      };
380
381      cpu@1 {
382        device_type = "cpu";
383        compatible = "arm,cortex-a15";
384        reg = <0x1>;
385      };
386
387      cpu@100 {
388        device_type = "cpu";
389        compatible = "arm,cortex-a7";
390        reg = <0x100>;
391      };
392
393      cpu@101 {
394        device_type = "cpu";
395        compatible = "arm,cortex-a7";
396        reg = <0x101>;
397      };
398    };
399
400  - |
401    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
402    cpus {
403      #size-cells = <0>;
404      #address-cells = <1>;
405
406      cpu@0 {
407        device_type = "cpu";
408        compatible = "arm,cortex-a8";
409        reg = <0x0>;
410      };
411    };
412
413  - |
414    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
415    cpus {
416      #size-cells = <0>;
417      #address-cells = <1>;
418
419      cpu@0 {
420        device_type = "cpu";
421        compatible = "arm,arm926ej-s";
422        reg = <0x0>;
423      };
424    };
425
426  - |
427    //  Example 4 (ARM Cortex-A57 64-bit system):
428    cpus {
429      #size-cells = <0>;
430      #address-cells = <2>;
431
432      cpu@0 {
433        device_type = "cpu";
434        compatible = "arm,cortex-a57";
435        reg = <0x0 0x0>;
436        enable-method = "spin-table";
437        cpu-release-addr = <0 0x20000000>;
438      };
439
440      cpu@1 {
441        device_type = "cpu";
442        compatible = "arm,cortex-a57";
443        reg = <0x0 0x1>;
444        enable-method = "spin-table";
445        cpu-release-addr = <0 0x20000000>;
446      };
447
448      cpu@100 {
449        device_type = "cpu";
450        compatible = "arm,cortex-a57";
451        reg = <0x0 0x100>;
452        enable-method = "spin-table";
453        cpu-release-addr = <0 0x20000000>;
454      };
455
456      cpu@101 {
457        device_type = "cpu";
458        compatible = "arm,cortex-a57";
459        reg = <0x0 0x101>;
460        enable-method = "spin-table";
461        cpu-release-addr = <0 0x20000000>;
462      };
463
464      cpu@10000 {
465        device_type = "cpu";
466        compatible = "arm,cortex-a57";
467        reg = <0x0 0x10000>;
468        enable-method = "spin-table";
469        cpu-release-addr = <0 0x20000000>;
470      };
471
472      cpu@10001 {
473        device_type = "cpu";
474        compatible = "arm,cortex-a57";
475        reg = <0x0 0x10001>;
476        enable-method = "spin-table";
477        cpu-release-addr = <0 0x20000000>;
478      };
479
480      cpu@10100 {
481        device_type = "cpu";
482        compatible = "arm,cortex-a57";
483        reg = <0x0 0x10100>;
484        enable-method = "spin-table";
485        cpu-release-addr = <0 0x20000000>;
486      };
487
488      cpu@10101 {
489        device_type = "cpu";
490        compatible = "arm,cortex-a57";
491        reg = <0x0 0x10101>;
492        enable-method = "spin-table";
493        cpu-release-addr = <0 0x20000000>;
494      };
495
496      cpu@100000000 {
497        device_type = "cpu";
498        compatible = "arm,cortex-a57";
499        reg = <0x1 0x0>;
500        enable-method = "spin-table";
501        cpu-release-addr = <0 0x20000000>;
502      };
503
504      cpu@100000001 {
505        device_type = "cpu";
506        compatible = "arm,cortex-a57";
507        reg = <0x1 0x1>;
508        enable-method = "spin-table";
509        cpu-release-addr = <0 0x20000000>;
510      };
511
512      cpu@100000100 {
513        device_type = "cpu";
514        compatible = "arm,cortex-a57";
515        reg = <0x1 0x100>;
516        enable-method = "spin-table";
517        cpu-release-addr = <0 0x20000000>;
518      };
519
520      cpu@100000101 {
521        device_type = "cpu";
522        compatible = "arm,cortex-a57";
523        reg = <0x1 0x101>;
524        enable-method = "spin-table";
525        cpu-release-addr = <0 0x20000000>;
526      };
527
528      cpu@100010000 {
529        device_type = "cpu";
530        compatible = "arm,cortex-a57";
531        reg = <0x1 0x10000>;
532        enable-method = "spin-table";
533        cpu-release-addr = <0 0x20000000>;
534      };
535
536      cpu@100010001 {
537        device_type = "cpu";
538        compatible = "arm,cortex-a57";
539        reg = <0x1 0x10001>;
540        enable-method = "spin-table";
541        cpu-release-addr = <0 0x20000000>;
542      };
543
544      cpu@100010100 {
545        device_type = "cpu";
546        compatible = "arm,cortex-a57";
547        reg = <0x1 0x10100>;
548        enable-method = "spin-table";
549        cpu-release-addr = <0 0x20000000>;
550      };
551
552      cpu@100010101 {
553        device_type = "cpu";
554        compatible = "arm,cortex-a57";
555        reg = <0x1 0x10101>;
556        enable-method = "spin-table";
557        cpu-release-addr = <0 0x20000000>;
558      };
559    };
560...
561