1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a53
127      - arm,cortex-a55
128      - arm,cortex-a57
129      - arm,cortex-a72
130      - arm,cortex-a73
131      - arm,cortex-m0
132      - arm,cortex-m0+
133      - arm,cortex-m1
134      - arm,cortex-m3
135      - arm,cortex-m4
136      - arm,cortex-r4
137      - arm,cortex-r5
138      - arm,cortex-r7
139      - brcm,brahma-b15
140      - brcm,brahma-b53
141      - brcm,vulcan
142      - cavium,thunder
143      - cavium,thunder2
144      - faraday,fa526
145      - intel,sa110
146      - intel,sa1100
147      - marvell,feroceon
148      - marvell,mohawk
149      - marvell,pj4a
150      - marvell,pj4b
151      - marvell,sheeva-v5
152      - marvell,sheeva-v7
153      - nvidia,tegra132-denver
154      - nvidia,tegra186-denver
155      - nvidia,tegra194-carmel
156      - qcom,krait
157      - qcom,kryo
158      - qcom,kryo385
159      - qcom,kryo485
160      - qcom,scorpion
161
162  enable-method:
163    allOf:
164      - $ref: '/schemas/types.yaml#/definitions/string'
165      - oneOf:
166          # On ARM v8 64-bit this property is required
167          - enum:
168              - psci
169              - spin-table
170          # On ARM 32-bit systems this property is optional
171          - enum:
172              - actions,s500-smp
173              - allwinner,sun6i-a31
174              - allwinner,sun8i-a23
175              - allwinner,sun9i-a80-smp
176              - allwinner,sun8i-a83t-smp
177              - amlogic,meson8-smp
178              - amlogic,meson8b-smp
179              - arm,realview-smp
180              - aspeed,ast2600-smp
181              - brcm,bcm11351-cpu-method
182              - brcm,bcm23550
183              - brcm,bcm2836-smp
184              - brcm,bcm63138
185              - brcm,bcm-nsp-smp
186              - brcm,brahma-b15
187              - marvell,armada-375-smp
188              - marvell,armada-380-smp
189              - marvell,armada-390-smp
190              - marvell,armada-xp-smp
191              - marvell,98dx3236-smp
192              - marvell,mmp3-smp
193              - mediatek,mt6589-smp
194              - mediatek,mt81xx-tz-smp
195              - qcom,gcc-msm8660
196              - qcom,kpss-acc-v1
197              - qcom,kpss-acc-v2
198              - renesas,apmu
199              - renesas,r9a06g032-smp
200              - rockchip,rk3036-smp
201              - rockchip,rk3066-smp
202              - socionext,milbeaut-m10v-smp
203              - ste,dbx500-smp
204
205  cpu-release-addr:
206    $ref: '/schemas/types.yaml#/definitions/uint64'
207
208    description:
209      Required for systems that have an "enable-method"
210        property value of "spin-table".
211      On ARM v8 64-bit systems must be a two cell
212        property identifying a 64-bit zero-initialised
213        memory location.
214
215  cpu-idle-states:
216    $ref: '/schemas/types.yaml#/definitions/phandle-array'
217    description: |
218      List of phandles to idle state nodes supported
219      by this cpu (see ./idle-states.txt).
220
221  capacity-dmips-mhz:
222    $ref: '/schemas/types.yaml#/definitions/uint32'
223    description:
224      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
225      DMIPS/MHz, relative to highest capacity-dmips-mhz
226      in the system.
227
228  dynamic-power-coefficient:
229    $ref: '/schemas/types.yaml#/definitions/uint32'
230    description:
231      A u32 value that represents the running time dynamic
232      power coefficient in units of uW/MHz/V^2. The
233      coefficient can either be calculated from power
234      measurements or derived by analysis.
235
236      The dynamic power consumption of the CPU  is
237      proportional to the square of the Voltage (V) and
238      the clock frequency (f). The coefficient is used to
239      calculate the dynamic power as below -
240
241      Pdyn = dynamic-power-coefficient * V^2 * f
242
243      where voltage is in V, frequency is in MHz.
244
245  qcom,saw:
246    $ref: '/schemas/types.yaml#/definitions/phandle'
247    description: |
248      Specifies the SAW* node associated with this CPU.
249
250      Required for systems that have an "enable-method" property
251      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
252
253      * arm/msm/qcom,saw2.txt
254
255  qcom,acc:
256    $ref: '/schemas/types.yaml#/definitions/phandle'
257    description: |
258      Specifies the ACC* node associated with this CPU.
259
260      Required for systems that have an "enable-method" property
261      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
262
263      * arm/msm/qcom,kpss-acc.txt
264
265  rockchip,pmu:
266    $ref: '/schemas/types.yaml#/definitions/phandle'
267    description: |
268      Specifies the syscon node controlling the cpu core power domains.
269
270      Optional for systems that have an "enable-method"
271      property value of "rockchip,rk3066-smp"
272      While optional, it is the preferred way to get access to
273      the cpu-core power-domains.
274
275required:
276  - device_type
277  - reg
278  - compatible
279
280dependencies:
281  rockchip,pmu: [enable-method]
282
283examples:
284  - |
285    cpus {
286      #size-cells = <0>;
287      #address-cells = <1>;
288
289      cpu@0 {
290        device_type = "cpu";
291        compatible = "arm,cortex-a15";
292        reg = <0x0>;
293      };
294
295      cpu@1 {
296        device_type = "cpu";
297        compatible = "arm,cortex-a15";
298        reg = <0x1>;
299      };
300
301      cpu@100 {
302        device_type = "cpu";
303        compatible = "arm,cortex-a7";
304        reg = <0x100>;
305      };
306
307      cpu@101 {
308        device_type = "cpu";
309        compatible = "arm,cortex-a7";
310        reg = <0x101>;
311      };
312    };
313
314  - |
315    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
316    cpus {
317      #size-cells = <0>;
318      #address-cells = <1>;
319
320      cpu@0 {
321        device_type = "cpu";
322        compatible = "arm,cortex-a8";
323        reg = <0x0>;
324      };
325    };
326
327  - |
328    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
329    cpus {
330      #size-cells = <0>;
331      #address-cells = <1>;
332
333      cpu@0 {
334        device_type = "cpu";
335        compatible = "arm,arm926ej-s";
336        reg = <0x0>;
337      };
338    };
339
340  - |
341    //  Example 4 (ARM Cortex-A57 64-bit system):
342    cpus {
343      #size-cells = <0>;
344      #address-cells = <2>;
345
346      cpu@0 {
347        device_type = "cpu";
348        compatible = "arm,cortex-a57";
349        reg = <0x0 0x0>;
350        enable-method = "spin-table";
351        cpu-release-addr = <0 0x20000000>;
352      };
353
354      cpu@1 {
355        device_type = "cpu";
356        compatible = "arm,cortex-a57";
357        reg = <0x0 0x1>;
358        enable-method = "spin-table";
359        cpu-release-addr = <0 0x20000000>;
360      };
361
362      cpu@100 {
363        device_type = "cpu";
364        compatible = "arm,cortex-a57";
365        reg = <0x0 0x100>;
366        enable-method = "spin-table";
367        cpu-release-addr = <0 0x20000000>;
368      };
369
370      cpu@101 {
371        device_type = "cpu";
372        compatible = "arm,cortex-a57";
373        reg = <0x0 0x101>;
374        enable-method = "spin-table";
375        cpu-release-addr = <0 0x20000000>;
376      };
377
378      cpu@10000 {
379        device_type = "cpu";
380        compatible = "arm,cortex-a57";
381        reg = <0x0 0x10000>;
382        enable-method = "spin-table";
383        cpu-release-addr = <0 0x20000000>;
384      };
385
386      cpu@10001 {
387        device_type = "cpu";
388        compatible = "arm,cortex-a57";
389        reg = <0x0 0x10001>;
390        enable-method = "spin-table";
391        cpu-release-addr = <0 0x20000000>;
392      };
393
394      cpu@10100 {
395        device_type = "cpu";
396        compatible = "arm,cortex-a57";
397        reg = <0x0 0x10100>;
398        enable-method = "spin-table";
399        cpu-release-addr = <0 0x20000000>;
400      };
401
402      cpu@10101 {
403        device_type = "cpu";
404        compatible = "arm,cortex-a57";
405        reg = <0x0 0x10101>;
406        enable-method = "spin-table";
407        cpu-release-addr = <0 0x20000000>;
408      };
409
410      cpu@100000000 {
411        device_type = "cpu";
412        compatible = "arm,cortex-a57";
413        reg = <0x1 0x0>;
414        enable-method = "spin-table";
415        cpu-release-addr = <0 0x20000000>;
416      };
417
418      cpu@100000001 {
419        device_type = "cpu";
420        compatible = "arm,cortex-a57";
421        reg = <0x1 0x1>;
422        enable-method = "spin-table";
423        cpu-release-addr = <0 0x20000000>;
424      };
425
426      cpu@100000100 {
427        device_type = "cpu";
428        compatible = "arm,cortex-a57";
429        reg = <0x1 0x100>;
430        enable-method = "spin-table";
431        cpu-release-addr = <0 0x20000000>;
432      };
433
434      cpu@100000101 {
435        device_type = "cpu";
436        compatible = "arm,cortex-a57";
437        reg = <0x1 0x101>;
438        enable-method = "spin-table";
439        cpu-release-addr = <0 0x20000000>;
440      };
441
442      cpu@100010000 {
443        device_type = "cpu";
444        compatible = "arm,cortex-a57";
445        reg = <0x1 0x10000>;
446        enable-method = "spin-table";
447        cpu-release-addr = <0 0x20000000>;
448      };
449
450      cpu@100010001 {
451        device_type = "cpu";
452        compatible = "arm,cortex-a57";
453        reg = <0x1 0x10001>;
454        enable-method = "spin-table";
455        cpu-release-addr = <0 0x20000000>;
456      };
457
458      cpu@100010100 {
459        device_type = "cpu";
460        compatible = "arm,cortex-a57";
461        reg = <0x1 0x10100>;
462        enable-method = "spin-table";
463        cpu-release-addr = <0 0x20000000>;
464      };
465
466      cpu@100010101 {
467        device_type = "cpu";
468        compatible = "arm,cortex-a57";
469        reg = <0x1 0x10101>;
470        enable-method = "spin-table";
471        cpu-release-addr = <0 0x20000000>;
472      };
473    };
474...
475