1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs bindings 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,icestorm 89 - apple,firestorm 90 - arm,arm710t 91 - arm,arm720t 92 - arm,arm740t 93 - arm,arm7ej-s 94 - arm,arm7tdmi 95 - arm,arm7tdmi-s 96 - arm,arm9es 97 - arm,arm9ej-s 98 - arm,arm920t 99 - arm,arm922t 100 - arm,arm925 101 - arm,arm926e-s 102 - arm,arm926ej-s 103 - arm,arm940t 104 - arm,arm946e-s 105 - arm,arm966e-s 106 - arm,arm968e-s 107 - arm,arm9tdmi 108 - arm,arm1020e 109 - arm,arm1020t 110 - arm,arm1022e 111 - arm,arm1026ej-s 112 - arm,arm1136j-s 113 - arm,arm1136jf-s 114 - arm,arm1156t2-s 115 - arm,arm1156t2f-s 116 - arm,arm1176jzf 117 - arm,arm1176jz-s 118 - arm,arm1176jzf-s 119 - arm,arm11mpcore 120 - arm,armv8 # Only for s/w models 121 - arm,cortex-a5 122 - arm,cortex-a7 123 - arm,cortex-a8 124 - arm,cortex-a9 125 - arm,cortex-a12 126 - arm,cortex-a15 127 - arm,cortex-a17 128 - arm,cortex-a32 129 - arm,cortex-a34 130 - arm,cortex-a35 131 - arm,cortex-a53 132 - arm,cortex-a55 133 - arm,cortex-a57 134 - arm,cortex-a65 135 - arm,cortex-a72 136 - arm,cortex-a73 137 - arm,cortex-a75 138 - arm,cortex-a76 139 - arm,cortex-a77 140 - arm,cortex-a78 141 - arm,cortex-a510 142 - arm,cortex-a710 143 - arm,cortex-m0 144 - arm,cortex-m0+ 145 - arm,cortex-m1 146 - arm,cortex-m3 147 - arm,cortex-m4 148 - arm,cortex-r4 149 - arm,cortex-r5 150 - arm,cortex-r7 151 - arm,cortex-x1 152 - arm,cortex-x2 153 - arm,neoverse-e1 154 - arm,neoverse-n1 155 - arm,neoverse-n2 156 - arm,neoverse-v1 157 - brcm,brahma-b15 158 - brcm,brahma-b53 159 - brcm,vulcan 160 - cavium,thunder 161 - cavium,thunder2 162 - faraday,fa526 163 - intel,sa110 164 - intel,sa1100 165 - marvell,feroceon 166 - marvell,mohawk 167 - marvell,pj4a 168 - marvell,pj4b 169 - marvell,sheeva-v5 170 - marvell,sheeva-v7 171 - nvidia,tegra132-denver 172 - nvidia,tegra186-denver 173 - nvidia,tegra194-carmel 174 - qcom,krait 175 - qcom,kryo 176 - qcom,kryo250 177 - qcom,kryo260 178 - qcom,kryo280 179 - qcom,kryo385 180 - qcom,kryo468 181 - qcom,kryo485 182 - qcom,kryo560 183 - qcom,kryo570 184 - qcom,kryo685 185 - qcom,kryo780 186 - qcom,scorpion 187 188 enable-method: 189 $ref: '/schemas/types.yaml#/definitions/string' 190 oneOf: 191 # On ARM v8 64-bit this property is required 192 - enum: 193 - psci 194 - spin-table 195 # On ARM 32-bit systems this property is optional 196 - enum: 197 - actions,s500-smp 198 - allwinner,sun6i-a31 199 - allwinner,sun8i-a23 200 - allwinner,sun9i-a80-smp 201 - allwinner,sun8i-a83t-smp 202 - amlogic,meson8-smp 203 - amlogic,meson8b-smp 204 - arm,realview-smp 205 - aspeed,ast2600-smp 206 - brcm,bcm11351-cpu-method 207 - brcm,bcm23550 208 - brcm,bcm2836-smp 209 - brcm,bcm63138 210 - brcm,bcm-nsp-smp 211 - brcm,brahma-b15 212 - marvell,armada-375-smp 213 - marvell,armada-380-smp 214 - marvell,armada-390-smp 215 - marvell,armada-xp-smp 216 - marvell,98dx3236-smp 217 - marvell,mmp3-smp 218 - mediatek,mt6589-smp 219 - mediatek,mt81xx-tz-smp 220 - qcom,gcc-msm8660 221 - qcom,kpss-acc-v1 222 - qcom,kpss-acc-v2 223 - qcom,msm8226-smp 224 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 225 - qcom,msm8916-smp 226 - renesas,apmu 227 - renesas,r9a06g032-smp 228 - rockchip,rk3036-smp 229 - rockchip,rk3066-smp 230 - socionext,milbeaut-m10v-smp 231 - ste,dbx500-smp 232 - ti,am3352 233 - ti,am4372 234 235 cpu-release-addr: 236 $ref: '/schemas/types.yaml#/definitions/uint64' 237 238 description: 239 Required for systems that have an "enable-method" 240 property value of "spin-table". 241 On ARM v8 64-bit systems must be a two cell 242 property identifying a 64-bit zero-initialised 243 memory location. 244 245 cpu-idle-states: 246 $ref: '/schemas/types.yaml#/definitions/phandle-array' 247 description: | 248 List of phandles to idle state nodes supported 249 by this cpu (see ./idle-states.yaml). 250 251 capacity-dmips-mhz: 252 description: 253 u32 value representing CPU capacity (see ./cpu-capacity.txt) in 254 DMIPS/MHz, relative to highest capacity-dmips-mhz 255 in the system. 256 257 cci-control-port: true 258 259 dynamic-power-coefficient: 260 $ref: '/schemas/types.yaml#/definitions/uint32' 261 description: 262 A u32 value that represents the running time dynamic 263 power coefficient in units of uW/MHz/V^2. The 264 coefficient can either be calculated from power 265 measurements or derived by analysis. 266 267 The dynamic power consumption of the CPU is 268 proportional to the square of the Voltage (V) and 269 the clock frequency (f). The coefficient is used to 270 calculate the dynamic power as below - 271 272 Pdyn = dynamic-power-coefficient * V^2 * f 273 274 where voltage is in V, frequency is in MHz. 275 276 performance-domains: 277 maxItems: 1 278 description: 279 List of phandles and performance domain specifiers, as defined by 280 bindings of the performance domain provider. See also 281 dvfs/performance-domain.yaml. 282 283 power-domains: 284 description: 285 List of phandles and PM domain specifiers, as defined by bindings of the 286 PM domain provider (see also ../power_domain.txt). 287 288 power-domain-names: 289 description: 290 A list of power domain name strings sorted in the same order as the 291 power-domains property. 292 293 For PSCI based platforms, the name corresponding to the index of the PSCI 294 PM domain provider, must be "psci". 295 296 qcom,saw: 297 $ref: '/schemas/types.yaml#/definitions/phandle' 298 description: | 299 Specifies the SAW* node associated with this CPU. 300 301 Required for systems that have an "enable-method" property 302 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 303 304 * arm/msm/qcom,saw2.txt 305 306 qcom,acc: 307 $ref: '/schemas/types.yaml#/definitions/phandle' 308 description: | 309 Specifies the ACC* node associated with this CPU. 310 311 Required for systems that have an "enable-method" property 312 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 313 "qcom,msm8916-smp". 314 315 * arm/msm/qcom,kpss-acc.txt 316 317 rockchip,pmu: 318 $ref: '/schemas/types.yaml#/definitions/phandle' 319 description: | 320 Specifies the syscon node controlling the cpu core power domains. 321 322 Optional for systems that have an "enable-method" 323 property value of "rockchip,rk3066-smp" 324 While optional, it is the preferred way to get access to 325 the cpu-core power-domains. 326 327 secondary-boot-reg: 328 $ref: '/schemas/types.yaml#/definitions/uint32' 329 description: | 330 Required for systems that have an "enable-method" property value of 331 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 332 333 This includes the following SoCs: | 334 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 335 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 336 337 The secondary-boot-reg property is a u32 value that specifies the 338 physical address of the register used to request the ROM holding pen 339 code release a secondary CPU. The value written to the register is 340 formed by encoding the target CPU id into the low bits of the 341 physical start address it should jump to. 342 343if: 344 # If the enable-method property contains one of those values 345 properties: 346 enable-method: 347 contains: 348 enum: 349 - brcm,bcm11351-cpu-method 350 - brcm,bcm23550 351 - brcm,bcm-nsp-smp 352 # and if enable-method is present 353 required: 354 - enable-method 355 356then: 357 required: 358 - secondary-boot-reg 359 360required: 361 - device_type 362 - reg 363 - compatible 364 365dependencies: 366 rockchip,pmu: [enable-method] 367 368additionalProperties: true 369 370examples: 371 - | 372 cpus { 373 #size-cells = <0>; 374 #address-cells = <1>; 375 376 cpu@0 { 377 device_type = "cpu"; 378 compatible = "arm,cortex-a15"; 379 reg = <0x0>; 380 }; 381 382 cpu@1 { 383 device_type = "cpu"; 384 compatible = "arm,cortex-a15"; 385 reg = <0x1>; 386 }; 387 388 cpu@100 { 389 device_type = "cpu"; 390 compatible = "arm,cortex-a7"; 391 reg = <0x100>; 392 }; 393 394 cpu@101 { 395 device_type = "cpu"; 396 compatible = "arm,cortex-a7"; 397 reg = <0x101>; 398 }; 399 }; 400 401 - | 402 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 403 cpus { 404 #size-cells = <0>; 405 #address-cells = <1>; 406 407 cpu@0 { 408 device_type = "cpu"; 409 compatible = "arm,cortex-a8"; 410 reg = <0x0>; 411 }; 412 }; 413 414 - | 415 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 416 cpus { 417 #size-cells = <0>; 418 #address-cells = <1>; 419 420 cpu@0 { 421 device_type = "cpu"; 422 compatible = "arm,arm926ej-s"; 423 reg = <0x0>; 424 }; 425 }; 426 427 - | 428 // Example 4 (ARM Cortex-A57 64-bit system): 429 cpus { 430 #size-cells = <0>; 431 #address-cells = <2>; 432 433 cpu@0 { 434 device_type = "cpu"; 435 compatible = "arm,cortex-a57"; 436 reg = <0x0 0x0>; 437 enable-method = "spin-table"; 438 cpu-release-addr = <0 0x20000000>; 439 }; 440 441 cpu@1 { 442 device_type = "cpu"; 443 compatible = "arm,cortex-a57"; 444 reg = <0x0 0x1>; 445 enable-method = "spin-table"; 446 cpu-release-addr = <0 0x20000000>; 447 }; 448 449 cpu@100 { 450 device_type = "cpu"; 451 compatible = "arm,cortex-a57"; 452 reg = <0x0 0x100>; 453 enable-method = "spin-table"; 454 cpu-release-addr = <0 0x20000000>; 455 }; 456 457 cpu@101 { 458 device_type = "cpu"; 459 compatible = "arm,cortex-a57"; 460 reg = <0x0 0x101>; 461 enable-method = "spin-table"; 462 cpu-release-addr = <0 0x20000000>; 463 }; 464 465 cpu@10000 { 466 device_type = "cpu"; 467 compatible = "arm,cortex-a57"; 468 reg = <0x0 0x10000>; 469 enable-method = "spin-table"; 470 cpu-release-addr = <0 0x20000000>; 471 }; 472 473 cpu@10001 { 474 device_type = "cpu"; 475 compatible = "arm,cortex-a57"; 476 reg = <0x0 0x10001>; 477 enable-method = "spin-table"; 478 cpu-release-addr = <0 0x20000000>; 479 }; 480 481 cpu@10100 { 482 device_type = "cpu"; 483 compatible = "arm,cortex-a57"; 484 reg = <0x0 0x10100>; 485 enable-method = "spin-table"; 486 cpu-release-addr = <0 0x20000000>; 487 }; 488 489 cpu@10101 { 490 device_type = "cpu"; 491 compatible = "arm,cortex-a57"; 492 reg = <0x0 0x10101>; 493 enable-method = "spin-table"; 494 cpu-release-addr = <0 0x20000000>; 495 }; 496 497 cpu@100000000 { 498 device_type = "cpu"; 499 compatible = "arm,cortex-a57"; 500 reg = <0x1 0x0>; 501 enable-method = "spin-table"; 502 cpu-release-addr = <0 0x20000000>; 503 }; 504 505 cpu@100000001 { 506 device_type = "cpu"; 507 compatible = "arm,cortex-a57"; 508 reg = <0x1 0x1>; 509 enable-method = "spin-table"; 510 cpu-release-addr = <0 0x20000000>; 511 }; 512 513 cpu@100000100 { 514 device_type = "cpu"; 515 compatible = "arm,cortex-a57"; 516 reg = <0x1 0x100>; 517 enable-method = "spin-table"; 518 cpu-release-addr = <0 0x20000000>; 519 }; 520 521 cpu@100000101 { 522 device_type = "cpu"; 523 compatible = "arm,cortex-a57"; 524 reg = <0x1 0x101>; 525 enable-method = "spin-table"; 526 cpu-release-addr = <0 0x20000000>; 527 }; 528 529 cpu@100010000 { 530 device_type = "cpu"; 531 compatible = "arm,cortex-a57"; 532 reg = <0x1 0x10000>; 533 enable-method = "spin-table"; 534 cpu-release-addr = <0 0x20000000>; 535 }; 536 537 cpu@100010001 { 538 device_type = "cpu"; 539 compatible = "arm,cortex-a57"; 540 reg = <0x1 0x10001>; 541 enable-method = "spin-table"; 542 cpu-release-addr = <0 0x20000000>; 543 }; 544 545 cpu@100010100 { 546 device_type = "cpu"; 547 compatible = "arm,cortex-a57"; 548 reg = <0x1 0x10100>; 549 enable-method = "spin-table"; 550 cpu-release-addr = <0 0x20000000>; 551 }; 552 553 cpu@100010101 { 554 device_type = "cpu"; 555 compatible = "arm,cortex-a57"; 556 reg = <0x1 0x10101>; 557 enable-method = "spin-table"; 558 cpu-release-addr = <0 0x20000000>; 559 }; 560 }; 561... 562