1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a53
127      - arm,cortex-a57
128      - arm,cortex-a72
129      - arm,cortex-a73
130      - arm,cortex-m0
131      - arm,cortex-m0+
132      - arm,cortex-m1
133      - arm,cortex-m3
134      - arm,cortex-m4
135      - arm,cortex-r4
136      - arm,cortex-r5
137      - arm,cortex-r7
138      - brcm,brahma-b15
139      - brcm,brahma-b53
140      - brcm,vulcan
141      - cavium,thunder
142      - cavium,thunder2
143      - faraday,fa526
144      - intel,sa110
145      - intel,sa1100
146      - marvell,feroceon
147      - marvell,mohawk
148      - marvell,pj4a
149      - marvell,pj4b
150      - marvell,sheeva-v5
151      - marvell,sheeva-v7
152      - nvidia,tegra132-denver
153      - nvidia,tegra186-denver
154      - nvidia,tegra194-carmel
155      - qcom,krait
156      - qcom,kryo
157      - qcom,kryo385
158      - qcom,scorpion
159
160  enable-method:
161    allOf:
162      - $ref: '/schemas/types.yaml#/definitions/string'
163      - oneOf:
164          # On ARM v8 64-bit this property is required
165          - enum:
166              - psci
167              - spin-table
168          # On ARM 32-bit systems this property is optional
169          - enum:
170              - actions,s500-smp
171              - allwinner,sun6i-a31
172              - allwinner,sun8i-a23
173              - allwinner,sun9i-a80-smp
174              - allwinner,sun8i-a83t-smp
175              - amlogic,meson8-smp
176              - amlogic,meson8b-smp
177              - arm,realview-smp
178              - aspeed,ast2600-smp
179              - brcm,bcm11351-cpu-method
180              - brcm,bcm23550
181              - brcm,bcm2836-smp
182              - brcm,bcm63138
183              - brcm,bcm-nsp-smp
184              - brcm,brahma-b15
185              - marvell,armada-375-smp
186              - marvell,armada-380-smp
187              - marvell,armada-390-smp
188              - marvell,armada-xp-smp
189              - marvell,98dx3236-smp
190              - mediatek,mt6589-smp
191              - mediatek,mt81xx-tz-smp
192              - qcom,gcc-msm8660
193              - qcom,kpss-acc-v1
194              - qcom,kpss-acc-v2
195              - renesas,apmu
196              - renesas,r9a06g032-smp
197              - rockchip,rk3036-smp
198              - rockchip,rk3066-smp
199              - socionext,milbeaut-m10v-smp
200              - ste,dbx500-smp
201
202  cpu-release-addr:
203    $ref: '/schemas/types.yaml#/definitions/uint64'
204
205    description:
206      Required for systems that have an "enable-method"
207        property value of "spin-table".
208      On ARM v8 64-bit systems must be a two cell
209        property identifying a 64-bit zero-initialised
210        memory location.
211
212  cpu-idle-states:
213    $ref: '/schemas/types.yaml#/definitions/phandle-array'
214    description: |
215      List of phandles to idle state nodes supported
216      by this cpu (see ./idle-states.txt).
217
218  capacity-dmips-mhz:
219    $ref: '/schemas/types.yaml#/definitions/uint32'
220    description:
221      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
222      DMIPS/MHz, relative to highest capacity-dmips-mhz
223      in the system.
224
225  dynamic-power-coefficient:
226    $ref: '/schemas/types.yaml#/definitions/uint32'
227    description:
228      A u32 value that represents the running time dynamic
229      power coefficient in units of uW/MHz/V^2. The
230      coefficient can either be calculated from power
231      measurements or derived by analysis.
232
233      The dynamic power consumption of the CPU  is
234      proportional to the square of the Voltage (V) and
235      the clock frequency (f). The coefficient is used to
236      calculate the dynamic power as below -
237
238      Pdyn = dynamic-power-coefficient * V^2 * f
239
240      where voltage is in V, frequency is in MHz.
241
242  qcom,saw:
243    $ref: '/schemas/types.yaml#/definitions/phandle'
244    description: |
245      Specifies the SAW* node associated with this CPU.
246
247      Required for systems that have an "enable-method" property
248      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
249
250      * arm/msm/qcom,saw2.txt
251
252  qcom,acc:
253    $ref: '/schemas/types.yaml#/definitions/phandle'
254    description: |
255      Specifies the ACC* node associated with this CPU.
256
257      Required for systems that have an "enable-method" property
258      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
259
260      * arm/msm/qcom,kpss-acc.txt
261
262  rockchip,pmu:
263    $ref: '/schemas/types.yaml#/definitions/phandle'
264    description: |
265      Specifies the syscon node controlling the cpu core power domains.
266
267      Optional for systems that have an "enable-method"
268      property value of "rockchip,rk3066-smp"
269      While optional, it is the preferred way to get access to
270      the cpu-core power-domains.
271
272required:
273  - device_type
274  - reg
275  - compatible
276
277dependencies:
278  rockchip,pmu: [enable-method]
279
280examples:
281  - |
282    cpus {
283      #size-cells = <0>;
284      #address-cells = <1>;
285
286      cpu@0 {
287        device_type = "cpu";
288        compatible = "arm,cortex-a15";
289        reg = <0x0>;
290      };
291
292      cpu@1 {
293        device_type = "cpu";
294        compatible = "arm,cortex-a15";
295        reg = <0x1>;
296      };
297
298      cpu@100 {
299        device_type = "cpu";
300        compatible = "arm,cortex-a7";
301        reg = <0x100>;
302      };
303
304      cpu@101 {
305        device_type = "cpu";
306        compatible = "arm,cortex-a7";
307        reg = <0x101>;
308      };
309    };
310
311  - |
312    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
313    cpus {
314      #size-cells = <0>;
315      #address-cells = <1>;
316
317      cpu@0 {
318        device_type = "cpu";
319        compatible = "arm,cortex-a8";
320        reg = <0x0>;
321      };
322    };
323
324  - |
325    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
326    cpus {
327      #size-cells = <0>;
328      #address-cells = <1>;
329
330      cpu@0 {
331        device_type = "cpu";
332        compatible = "arm,arm926ej-s";
333        reg = <0x0>;
334      };
335    };
336
337  - |
338    //  Example 4 (ARM Cortex-A57 64-bit system):
339    cpus {
340      #size-cells = <0>;
341      #address-cells = <2>;
342
343      cpu@0 {
344        device_type = "cpu";
345        compatible = "arm,cortex-a57";
346        reg = <0x0 0x0>;
347        enable-method = "spin-table";
348        cpu-release-addr = <0 0x20000000>;
349      };
350
351      cpu@1 {
352        device_type = "cpu";
353        compatible = "arm,cortex-a57";
354        reg = <0x0 0x1>;
355        enable-method = "spin-table";
356        cpu-release-addr = <0 0x20000000>;
357      };
358
359      cpu@100 {
360        device_type = "cpu";
361        compatible = "arm,cortex-a57";
362        reg = <0x0 0x100>;
363        enable-method = "spin-table";
364        cpu-release-addr = <0 0x20000000>;
365      };
366
367      cpu@101 {
368        device_type = "cpu";
369        compatible = "arm,cortex-a57";
370        reg = <0x0 0x101>;
371        enable-method = "spin-table";
372        cpu-release-addr = <0 0x20000000>;
373      };
374
375      cpu@10000 {
376        device_type = "cpu";
377        compatible = "arm,cortex-a57";
378        reg = <0x0 0x10000>;
379        enable-method = "spin-table";
380        cpu-release-addr = <0 0x20000000>;
381      };
382
383      cpu@10001 {
384        device_type = "cpu";
385        compatible = "arm,cortex-a57";
386        reg = <0x0 0x10001>;
387        enable-method = "spin-table";
388        cpu-release-addr = <0 0x20000000>;
389      };
390
391      cpu@10100 {
392        device_type = "cpu";
393        compatible = "arm,cortex-a57";
394        reg = <0x0 0x10100>;
395        enable-method = "spin-table";
396        cpu-release-addr = <0 0x20000000>;
397      };
398
399      cpu@10101 {
400        device_type = "cpu";
401        compatible = "arm,cortex-a57";
402        reg = <0x0 0x10101>;
403        enable-method = "spin-table";
404        cpu-release-addr = <0 0x20000000>;
405      };
406
407      cpu@100000000 {
408        device_type = "cpu";
409        compatible = "arm,cortex-a57";
410        reg = <0x1 0x0>;
411        enable-method = "spin-table";
412        cpu-release-addr = <0 0x20000000>;
413      };
414
415      cpu@100000001 {
416        device_type = "cpu";
417        compatible = "arm,cortex-a57";
418        reg = <0x1 0x1>;
419        enable-method = "spin-table";
420        cpu-release-addr = <0 0x20000000>;
421      };
422
423      cpu@100000100 {
424        device_type = "cpu";
425        compatible = "arm,cortex-a57";
426        reg = <0x1 0x100>;
427        enable-method = "spin-table";
428        cpu-release-addr = <0 0x20000000>;
429      };
430
431      cpu@100000101 {
432        device_type = "cpu";
433        compatible = "arm,cortex-a57";
434        reg = <0x1 0x101>;
435        enable-method = "spin-table";
436        cpu-release-addr = <0 0x20000000>;
437      };
438
439      cpu@100010000 {
440        device_type = "cpu";
441        compatible = "arm,cortex-a57";
442        reg = <0x1 0x10000>;
443        enable-method = "spin-table";
444        cpu-release-addr = <0 0x20000000>;
445      };
446
447      cpu@100010001 {
448        device_type = "cpu";
449        compatible = "arm,cortex-a57";
450        reg = <0x1 0x10001>;
451        enable-method = "spin-table";
452        cpu-release-addr = <0 0x20000000>;
453      };
454
455      cpu@100010100 {
456        device_type = "cpu";
457        compatible = "arm,cortex-a57";
458        reg = <0x1 0x10100>;
459        enable-method = "spin-table";
460        cpu-release-addr = <0 0x20000000>;
461      };
462
463      cpu@100010101 {
464        device_type = "cpu";
465        compatible = "arm,cortex-a57";
466        reg = <0x1 0x10101>;
467        enable-method = "spin-table";
468        cpu-release-addr = <0 0x20000000>;
469      };
470    };
471...
472