1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a78ae
142      - arm,cortex-a510
143      - arm,cortex-a710
144      - arm,cortex-m0
145      - arm,cortex-m0+
146      - arm,cortex-m1
147      - arm,cortex-m3
148      - arm,cortex-m4
149      - arm,cortex-r4
150      - arm,cortex-r5
151      - arm,cortex-r7
152      - arm,cortex-x1
153      - arm,cortex-x2
154      - arm,neoverse-e1
155      - arm,neoverse-n1
156      - arm,neoverse-n2
157      - arm,neoverse-v1
158      - brcm,brahma-b15
159      - brcm,brahma-b53
160      - brcm,vulcan
161      - cavium,thunder
162      - cavium,thunder2
163      - faraday,fa526
164      - intel,sa110
165      - intel,sa1100
166      - marvell,feroceon
167      - marvell,mohawk
168      - marvell,pj4a
169      - marvell,pj4b
170      - marvell,sheeva-v5
171      - marvell,sheeva-v7
172      - nvidia,tegra132-denver
173      - nvidia,tegra186-denver
174      - nvidia,tegra194-carmel
175      - qcom,krait
176      - qcom,kryo
177      - qcom,kryo240
178      - qcom,kryo250
179      - qcom,kryo260
180      - qcom,kryo280
181      - qcom,kryo360
182      - qcom,kryo385
183      - qcom,kryo468
184      - qcom,kryo485
185      - qcom,kryo560
186      - qcom,kryo570
187      - qcom,kryo660
188      - qcom,kryo685
189      - qcom,kryo780
190      - qcom,scorpion
191
192  enable-method:
193    $ref: '/schemas/types.yaml#/definitions/string'
194    oneOf:
195      # On ARM v8 64-bit this property is required
196      - enum:
197          - psci
198          - spin-table
199      # On ARM 32-bit systems this property is optional
200      - enum:
201          - actions,s500-smp
202          - allwinner,sun6i-a31
203          - allwinner,sun8i-a23
204          - allwinner,sun9i-a80-smp
205          - allwinner,sun8i-a83t-smp
206          - amlogic,meson8-smp
207          - amlogic,meson8b-smp
208          - arm,realview-smp
209          - aspeed,ast2600-smp
210          - brcm,bcm11351-cpu-method
211          - brcm,bcm23550
212          - brcm,bcm2836-smp
213          - brcm,bcm63138
214          - brcm,bcm-nsp-smp
215          - brcm,brahma-b15
216          - marvell,armada-375-smp
217          - marvell,armada-380-smp
218          - marvell,armada-390-smp
219          - marvell,armada-xp-smp
220          - marvell,98dx3236-smp
221          - marvell,mmp3-smp
222          - mediatek,mt6589-smp
223          - mediatek,mt81xx-tz-smp
224          - qcom,gcc-msm8660
225          - qcom,kpss-acc-v1
226          - qcom,kpss-acc-v2
227          - qcom,msm8226-smp
228          - qcom,msm8909-smp
229          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
230          - qcom,msm8916-smp
231          - renesas,apmu
232          - renesas,r9a06g032-smp
233          - rockchip,rk3036-smp
234          - rockchip,rk3066-smp
235          - socionext,milbeaut-m10v-smp
236          - ste,dbx500-smp
237          - ti,am3352
238          - ti,am4372
239
240  cpu-release-addr:
241    oneOf:
242      - $ref: '/schemas/types.yaml#/definitions/uint32'
243      - $ref: '/schemas/types.yaml#/definitions/uint64'
244    description:
245      The DT specification defines this as 64-bit always, but some 32-bit Arm
246      systems have used a 32-bit value which must be supported.
247      Required for systems that have an "enable-method"
248        property value of "spin-table".
249
250  cpu-idle-states:
251    $ref: '/schemas/types.yaml#/definitions/phandle-array'
252    items:
253      maxItems: 1
254    description: |
255      List of phandles to idle state nodes supported
256      by this cpu (see ./idle-states.yaml).
257
258  capacity-dmips-mhz:
259    description:
260      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
261      DMIPS/MHz, relative to highest capacity-dmips-mhz
262      in the system.
263
264  cci-control-port: true
265
266  dynamic-power-coefficient:
267    $ref: '/schemas/types.yaml#/definitions/uint32'
268    description:
269      A u32 value that represents the running time dynamic
270      power coefficient in units of uW/MHz/V^2. The
271      coefficient can either be calculated from power
272      measurements or derived by analysis.
273
274      The dynamic power consumption of the CPU  is
275      proportional to the square of the Voltage (V) and
276      the clock frequency (f). The coefficient is used to
277      calculate the dynamic power as below -
278
279      Pdyn = dynamic-power-coefficient * V^2 * f
280
281      where voltage is in V, frequency is in MHz.
282
283  performance-domains:
284    maxItems: 1
285    description:
286      List of phandles and performance domain specifiers, as defined by
287      bindings of the performance domain provider. See also
288      dvfs/performance-domain.yaml.
289
290  power-domains:
291    description:
292      List of phandles and PM domain specifiers, as defined by bindings of the
293      PM domain provider (see also ../power_domain.txt).
294
295  power-domain-names:
296    description:
297      A list of power domain name strings sorted in the same order as the
298      power-domains property.
299
300      For PSCI based platforms, the name corresponding to the index of the PSCI
301      PM domain provider, must be "psci".
302
303  qcom,saw:
304    $ref: '/schemas/types.yaml#/definitions/phandle'
305    description: |
306      Specifies the SAW* node associated with this CPU.
307
308      Required for systems that have an "enable-method" property
309      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
310
311      * arm/msm/qcom,saw2.txt
312
313  qcom,acc:
314    $ref: '/schemas/types.yaml#/definitions/phandle'
315    description: |
316      Specifies the ACC* node associated with this CPU.
317
318      Required for systems that have an "enable-method" property
319      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
320      "qcom,msm8916-smp".
321
322      * arm/msm/qcom,kpss-acc.txt
323
324  rockchip,pmu:
325    $ref: '/schemas/types.yaml#/definitions/phandle'
326    description: |
327      Specifies the syscon node controlling the cpu core power domains.
328
329      Optional for systems that have an "enable-method"
330      property value of "rockchip,rk3066-smp"
331      While optional, it is the preferred way to get access to
332      the cpu-core power-domains.
333
334  secondary-boot-reg:
335    $ref: '/schemas/types.yaml#/definitions/uint32'
336    description: |
337      Required for systems that have an "enable-method" property value of
338      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
339
340      This includes the following SoCs: |
341      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
342      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
343
344      The secondary-boot-reg property is a u32 value that specifies the
345      physical address of the register used to request the ROM holding pen
346      code release a secondary CPU. The value written to the register is
347      formed by encoding the target CPU id into the low bits of the
348      physical start address it should jump to.
349
350if:
351  # If the enable-method property contains one of those values
352  properties:
353    enable-method:
354      contains:
355        enum:
356          - brcm,bcm11351-cpu-method
357          - brcm,bcm23550
358          - brcm,bcm-nsp-smp
359  # and if enable-method is present
360  required:
361    - enable-method
362
363then:
364  required:
365    - secondary-boot-reg
366
367required:
368  - device_type
369  - reg
370  - compatible
371
372dependencies:
373  rockchip,pmu: [enable-method]
374
375additionalProperties: true
376
377examples:
378  - |
379    cpus {
380      #size-cells = <0>;
381      #address-cells = <1>;
382
383      cpu@0 {
384        device_type = "cpu";
385        compatible = "arm,cortex-a15";
386        reg = <0x0>;
387      };
388
389      cpu@1 {
390        device_type = "cpu";
391        compatible = "arm,cortex-a15";
392        reg = <0x1>;
393      };
394
395      cpu@100 {
396        device_type = "cpu";
397        compatible = "arm,cortex-a7";
398        reg = <0x100>;
399      };
400
401      cpu@101 {
402        device_type = "cpu";
403        compatible = "arm,cortex-a7";
404        reg = <0x101>;
405      };
406    };
407
408  - |
409    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
410    cpus {
411      #size-cells = <0>;
412      #address-cells = <1>;
413
414      cpu@0 {
415        device_type = "cpu";
416        compatible = "arm,cortex-a8";
417        reg = <0x0>;
418      };
419    };
420
421  - |
422    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
423    cpus {
424      #size-cells = <0>;
425      #address-cells = <1>;
426
427      cpu@0 {
428        device_type = "cpu";
429        compatible = "arm,arm926ej-s";
430        reg = <0x0>;
431      };
432    };
433
434  - |
435    //  Example 4 (ARM Cortex-A57 64-bit system):
436    cpus {
437      #size-cells = <0>;
438      #address-cells = <2>;
439
440      cpu@0 {
441        device_type = "cpu";
442        compatible = "arm,cortex-a57";
443        reg = <0x0 0x0>;
444        enable-method = "spin-table";
445        cpu-release-addr = <0 0x20000000>;
446      };
447
448      cpu@1 {
449        device_type = "cpu";
450        compatible = "arm,cortex-a57";
451        reg = <0x0 0x1>;
452        enable-method = "spin-table";
453        cpu-release-addr = <0 0x20000000>;
454      };
455
456      cpu@100 {
457        device_type = "cpu";
458        compatible = "arm,cortex-a57";
459        reg = <0x0 0x100>;
460        enable-method = "spin-table";
461        cpu-release-addr = <0 0x20000000>;
462      };
463
464      cpu@101 {
465        device_type = "cpu";
466        compatible = "arm,cortex-a57";
467        reg = <0x0 0x101>;
468        enable-method = "spin-table";
469        cpu-release-addr = <0 0x20000000>;
470      };
471
472      cpu@10000 {
473        device_type = "cpu";
474        compatible = "arm,cortex-a57";
475        reg = <0x0 0x10000>;
476        enable-method = "spin-table";
477        cpu-release-addr = <0 0x20000000>;
478      };
479
480      cpu@10001 {
481        device_type = "cpu";
482        compatible = "arm,cortex-a57";
483        reg = <0x0 0x10001>;
484        enable-method = "spin-table";
485        cpu-release-addr = <0 0x20000000>;
486      };
487
488      cpu@10100 {
489        device_type = "cpu";
490        compatible = "arm,cortex-a57";
491        reg = <0x0 0x10100>;
492        enable-method = "spin-table";
493        cpu-release-addr = <0 0x20000000>;
494      };
495
496      cpu@10101 {
497        device_type = "cpu";
498        compatible = "arm,cortex-a57";
499        reg = <0x0 0x10101>;
500        enable-method = "spin-table";
501        cpu-release-addr = <0 0x20000000>;
502      };
503
504      cpu@100000000 {
505        device_type = "cpu";
506        compatible = "arm,cortex-a57";
507        reg = <0x1 0x0>;
508        enable-method = "spin-table";
509        cpu-release-addr = <0 0x20000000>;
510      };
511
512      cpu@100000001 {
513        device_type = "cpu";
514        compatible = "arm,cortex-a57";
515        reg = <0x1 0x1>;
516        enable-method = "spin-table";
517        cpu-release-addr = <0 0x20000000>;
518      };
519
520      cpu@100000100 {
521        device_type = "cpu";
522        compatible = "arm,cortex-a57";
523        reg = <0x1 0x100>;
524        enable-method = "spin-table";
525        cpu-release-addr = <0 0x20000000>;
526      };
527
528      cpu@100000101 {
529        device_type = "cpu";
530        compatible = "arm,cortex-a57";
531        reg = <0x1 0x101>;
532        enable-method = "spin-table";
533        cpu-release-addr = <0 0x20000000>;
534      };
535
536      cpu@100010000 {
537        device_type = "cpu";
538        compatible = "arm,cortex-a57";
539        reg = <0x1 0x10000>;
540        enable-method = "spin-table";
541        cpu-release-addr = <0 0x20000000>;
542      };
543
544      cpu@100010001 {
545        device_type = "cpu";
546        compatible = "arm,cortex-a57";
547        reg = <0x1 0x10001>;
548        enable-method = "spin-table";
549        cpu-release-addr = <0 0x20000000>;
550      };
551
552      cpu@100010100 {
553        device_type = "cpu";
554        compatible = "arm,cortex-a57";
555        reg = <0x1 0x10100>;
556        enable-method = "spin-table";
557        cpu-release-addr = <0 0x20000000>;
558      };
559
560      cpu@100010101 {
561        device_type = "cpu";
562        compatible = "arm,cortex-a57";
563        reg = <0x1 0x10101>;
564        enable-method = "spin-table";
565        cpu-release-addr = <0 0x20000000>;
566      };
567    };
568...
569