1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a510
142      - arm,cortex-a710
143      - arm,cortex-m0
144      - arm,cortex-m0+
145      - arm,cortex-m1
146      - arm,cortex-m3
147      - arm,cortex-m4
148      - arm,cortex-r4
149      - arm,cortex-r5
150      - arm,cortex-r7
151      - arm,cortex-x1
152      - arm,cortex-x2
153      - arm,neoverse-e1
154      - arm,neoverse-n1
155      - arm,neoverse-n2
156      - arm,neoverse-v1
157      - brcm,brahma-b15
158      - brcm,brahma-b53
159      - brcm,vulcan
160      - cavium,thunder
161      - cavium,thunder2
162      - faraday,fa526
163      - intel,sa110
164      - intel,sa1100
165      - marvell,feroceon
166      - marvell,mohawk
167      - marvell,pj4a
168      - marvell,pj4b
169      - marvell,sheeva-v5
170      - marvell,sheeva-v7
171      - nvidia,tegra132-denver
172      - nvidia,tegra186-denver
173      - nvidia,tegra194-carmel
174      - qcom,krait
175      - qcom,kryo
176      - qcom,kryo260
177      - qcom,kryo280
178      - qcom,kryo385
179      - qcom,kryo468
180      - qcom,kryo485
181      - qcom,kryo560
182      - qcom,kryo570
183      - qcom,kryo685
184      - qcom,scorpion
185
186  enable-method:
187    $ref: '/schemas/types.yaml#/definitions/string'
188    oneOf:
189      # On ARM v8 64-bit this property is required
190      - enum:
191          - psci
192          - spin-table
193      # On ARM 32-bit systems this property is optional
194      - enum:
195          - actions,s500-smp
196          - allwinner,sun6i-a31
197          - allwinner,sun8i-a23
198          - allwinner,sun9i-a80-smp
199          - allwinner,sun8i-a83t-smp
200          - amlogic,meson8-smp
201          - amlogic,meson8b-smp
202          - arm,realview-smp
203          - aspeed,ast2600-smp
204          - brcm,bcm11351-cpu-method
205          - brcm,bcm23550
206          - brcm,bcm2836-smp
207          - brcm,bcm63138
208          - brcm,bcm-nsp-smp
209          - brcm,brahma-b15
210          - marvell,armada-375-smp
211          - marvell,armada-380-smp
212          - marvell,armada-390-smp
213          - marvell,armada-xp-smp
214          - marvell,98dx3236-smp
215          - marvell,mmp3-smp
216          - mediatek,mt6589-smp
217          - mediatek,mt81xx-tz-smp
218          - qcom,gcc-msm8660
219          - qcom,kpss-acc-v1
220          - qcom,kpss-acc-v2
221          - qcom,msm8226-smp
222          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
223          - qcom,msm8916-smp
224          - renesas,apmu
225          - renesas,r9a06g032-smp
226          - rockchip,rk3036-smp
227          - rockchip,rk3066-smp
228          - socionext,milbeaut-m10v-smp
229          - ste,dbx500-smp
230          - ti,am3352
231          - ti,am4372
232
233  cpu-release-addr:
234    $ref: '/schemas/types.yaml#/definitions/uint64'
235
236    description:
237      Required for systems that have an "enable-method"
238        property value of "spin-table".
239      On ARM v8 64-bit systems must be a two cell
240        property identifying a 64-bit zero-initialised
241        memory location.
242
243  cpu-idle-states:
244    $ref: '/schemas/types.yaml#/definitions/phandle-array'
245    description: |
246      List of phandles to idle state nodes supported
247      by this cpu (see ./idle-states.yaml).
248
249  capacity-dmips-mhz:
250    description:
251      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
252      DMIPS/MHz, relative to highest capacity-dmips-mhz
253      in the system.
254
255  cci-control-port: true
256
257  dynamic-power-coefficient:
258    $ref: '/schemas/types.yaml#/definitions/uint32'
259    description:
260      A u32 value that represents the running time dynamic
261      power coefficient in units of uW/MHz/V^2. The
262      coefficient can either be calculated from power
263      measurements or derived by analysis.
264
265      The dynamic power consumption of the CPU  is
266      proportional to the square of the Voltage (V) and
267      the clock frequency (f). The coefficient is used to
268      calculate the dynamic power as below -
269
270      Pdyn = dynamic-power-coefficient * V^2 * f
271
272      where voltage is in V, frequency is in MHz.
273
274  performance-domains:
275    maxItems: 1
276    description:
277      List of phandles and performance domain specifiers, as defined by
278      bindings of the performance domain provider. See also
279      dvfs/performance-domain.yaml.
280
281  power-domains:
282    description:
283      List of phandles and PM domain specifiers, as defined by bindings of the
284      PM domain provider (see also ../power_domain.txt).
285
286  power-domain-names:
287    description:
288      A list of power domain name strings sorted in the same order as the
289      power-domains property.
290
291      For PSCI based platforms, the name corresponding to the index of the PSCI
292      PM domain provider, must be "psci".
293
294  qcom,saw:
295    $ref: '/schemas/types.yaml#/definitions/phandle'
296    description: |
297      Specifies the SAW* node associated with this CPU.
298
299      Required for systems that have an "enable-method" property
300      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
301
302      * arm/msm/qcom,saw2.txt
303
304  qcom,acc:
305    $ref: '/schemas/types.yaml#/definitions/phandle'
306    description: |
307      Specifies the ACC* node associated with this CPU.
308
309      Required for systems that have an "enable-method" property
310      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
311      "qcom,msm8916-smp".
312
313      * arm/msm/qcom,kpss-acc.txt
314
315  rockchip,pmu:
316    $ref: '/schemas/types.yaml#/definitions/phandle'
317    description: |
318      Specifies the syscon node controlling the cpu core power domains.
319
320      Optional for systems that have an "enable-method"
321      property value of "rockchip,rk3066-smp"
322      While optional, it is the preferred way to get access to
323      the cpu-core power-domains.
324
325  secondary-boot-reg:
326    $ref: '/schemas/types.yaml#/definitions/uint32'
327    description: |
328      Required for systems that have an "enable-method" property value of
329      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
330
331      This includes the following SoCs: |
332      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
333      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
334
335      The secondary-boot-reg property is a u32 value that specifies the
336      physical address of the register used to request the ROM holding pen
337      code release a secondary CPU. The value written to the register is
338      formed by encoding the target CPU id into the low bits of the
339      physical start address it should jump to.
340
341if:
342  # If the enable-method property contains one of those values
343  properties:
344    enable-method:
345      contains:
346        enum:
347          - brcm,bcm11351-cpu-method
348          - brcm,bcm23550
349          - brcm,bcm-nsp-smp
350  # and if enable-method is present
351  required:
352    - enable-method
353
354then:
355  required:
356    - secondary-boot-reg
357
358required:
359  - device_type
360  - reg
361  - compatible
362
363dependencies:
364  rockchip,pmu: [enable-method]
365
366additionalProperties: true
367
368examples:
369  - |
370    cpus {
371      #size-cells = <0>;
372      #address-cells = <1>;
373
374      cpu@0 {
375        device_type = "cpu";
376        compatible = "arm,cortex-a15";
377        reg = <0x0>;
378      };
379
380      cpu@1 {
381        device_type = "cpu";
382        compatible = "arm,cortex-a15";
383        reg = <0x1>;
384      };
385
386      cpu@100 {
387        device_type = "cpu";
388        compatible = "arm,cortex-a7";
389        reg = <0x100>;
390      };
391
392      cpu@101 {
393        device_type = "cpu";
394        compatible = "arm,cortex-a7";
395        reg = <0x101>;
396      };
397    };
398
399  - |
400    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
401    cpus {
402      #size-cells = <0>;
403      #address-cells = <1>;
404
405      cpu@0 {
406        device_type = "cpu";
407        compatible = "arm,cortex-a8";
408        reg = <0x0>;
409      };
410    };
411
412  - |
413    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
414    cpus {
415      #size-cells = <0>;
416      #address-cells = <1>;
417
418      cpu@0 {
419        device_type = "cpu";
420        compatible = "arm,arm926ej-s";
421        reg = <0x0>;
422      };
423    };
424
425  - |
426    //  Example 4 (ARM Cortex-A57 64-bit system):
427    cpus {
428      #size-cells = <0>;
429      #address-cells = <2>;
430
431      cpu@0 {
432        device_type = "cpu";
433        compatible = "arm,cortex-a57";
434        reg = <0x0 0x0>;
435        enable-method = "spin-table";
436        cpu-release-addr = <0 0x20000000>;
437      };
438
439      cpu@1 {
440        device_type = "cpu";
441        compatible = "arm,cortex-a57";
442        reg = <0x0 0x1>;
443        enable-method = "spin-table";
444        cpu-release-addr = <0 0x20000000>;
445      };
446
447      cpu@100 {
448        device_type = "cpu";
449        compatible = "arm,cortex-a57";
450        reg = <0x0 0x100>;
451        enable-method = "spin-table";
452        cpu-release-addr = <0 0x20000000>;
453      };
454
455      cpu@101 {
456        device_type = "cpu";
457        compatible = "arm,cortex-a57";
458        reg = <0x0 0x101>;
459        enable-method = "spin-table";
460        cpu-release-addr = <0 0x20000000>;
461      };
462
463      cpu@10000 {
464        device_type = "cpu";
465        compatible = "arm,cortex-a57";
466        reg = <0x0 0x10000>;
467        enable-method = "spin-table";
468        cpu-release-addr = <0 0x20000000>;
469      };
470
471      cpu@10001 {
472        device_type = "cpu";
473        compatible = "arm,cortex-a57";
474        reg = <0x0 0x10001>;
475        enable-method = "spin-table";
476        cpu-release-addr = <0 0x20000000>;
477      };
478
479      cpu@10100 {
480        device_type = "cpu";
481        compatible = "arm,cortex-a57";
482        reg = <0x0 0x10100>;
483        enable-method = "spin-table";
484        cpu-release-addr = <0 0x20000000>;
485      };
486
487      cpu@10101 {
488        device_type = "cpu";
489        compatible = "arm,cortex-a57";
490        reg = <0x0 0x10101>;
491        enable-method = "spin-table";
492        cpu-release-addr = <0 0x20000000>;
493      };
494
495      cpu@100000000 {
496        device_type = "cpu";
497        compatible = "arm,cortex-a57";
498        reg = <0x1 0x0>;
499        enable-method = "spin-table";
500        cpu-release-addr = <0 0x20000000>;
501      };
502
503      cpu@100000001 {
504        device_type = "cpu";
505        compatible = "arm,cortex-a57";
506        reg = <0x1 0x1>;
507        enable-method = "spin-table";
508        cpu-release-addr = <0 0x20000000>;
509      };
510
511      cpu@100000100 {
512        device_type = "cpu";
513        compatible = "arm,cortex-a57";
514        reg = <0x1 0x100>;
515        enable-method = "spin-table";
516        cpu-release-addr = <0 0x20000000>;
517      };
518
519      cpu@100000101 {
520        device_type = "cpu";
521        compatible = "arm,cortex-a57";
522        reg = <0x1 0x101>;
523        enable-method = "spin-table";
524        cpu-release-addr = <0 0x20000000>;
525      };
526
527      cpu@100010000 {
528        device_type = "cpu";
529        compatible = "arm,cortex-a57";
530        reg = <0x1 0x10000>;
531        enable-method = "spin-table";
532        cpu-release-addr = <0 0x20000000>;
533      };
534
535      cpu@100010001 {
536        device_type = "cpu";
537        compatible = "arm,cortex-a57";
538        reg = <0x1 0x10001>;
539        enable-method = "spin-table";
540        cpu-release-addr = <0 0x20000000>;
541      };
542
543      cpu@100010100 {
544        device_type = "cpu";
545        compatible = "arm,cortex-a57";
546        reg = <0x1 0x10100>;
547        enable-method = "spin-table";
548        cpu-release-addr = <0 0x20000000>;
549      };
550
551      cpu@100010101 {
552        device_type = "cpu";
553        compatible = "arm,cortex-a57";
554        reg = <0x1 0x10101>;
555        enable-method = "spin-table";
556        cpu-release-addr = <0 0x20000000>;
557      };
558    };
559...
560