1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a32
127      - arm,cortex-a34
128      - arm,cortex-a35
129      - arm,cortex-a53
130      - arm,cortex-a55
131      - arm,cortex-a57
132      - arm,cortex-a65
133      - arm,cortex-a72
134      - arm,cortex-a73
135      - arm,cortex-a75
136      - arm,cortex-a76
137      - arm,cortex-a77
138      - arm,cortex-m0
139      - arm,cortex-m0+
140      - arm,cortex-m1
141      - arm,cortex-m3
142      - arm,cortex-m4
143      - arm,cortex-r4
144      - arm,cortex-r5
145      - arm,cortex-r7
146      - arm,neoverse-e1
147      - arm,neoverse-n1
148      - brcm,brahma-b15
149      - brcm,brahma-b53
150      - brcm,vulcan
151      - cavium,thunder
152      - cavium,thunder2
153      - faraday,fa526
154      - intel,sa110
155      - intel,sa1100
156      - marvell,feroceon
157      - marvell,mohawk
158      - marvell,pj4a
159      - marvell,pj4b
160      - marvell,sheeva-v5
161      - marvell,sheeva-v7
162      - nvidia,tegra132-denver
163      - nvidia,tegra186-denver
164      - nvidia,tegra194-carmel
165      - qcom,krait
166      - qcom,kryo
167      - qcom,kryo260
168      - qcom,kryo280
169      - qcom,kryo385
170      - qcom,kryo485
171      - qcom,scorpion
172
173  enable-method:
174    allOf:
175      - $ref: '/schemas/types.yaml#/definitions/string'
176      - oneOf:
177          # On ARM v8 64-bit this property is required
178          - enum:
179              - psci
180              - spin-table
181          # On ARM 32-bit systems this property is optional
182          - enum:
183              - actions,s500-smp
184              - allwinner,sun6i-a31
185              - allwinner,sun8i-a23
186              - allwinner,sun9i-a80-smp
187              - allwinner,sun8i-a83t-smp
188              - amlogic,meson8-smp
189              - amlogic,meson8b-smp
190              - arm,realview-smp
191              - aspeed,ast2600-smp
192              - brcm,bcm11351-cpu-method
193              - brcm,bcm23550
194              - brcm,bcm2836-smp
195              - brcm,bcm63138
196              - brcm,bcm-nsp-smp
197              - brcm,brahma-b15
198              - marvell,armada-375-smp
199              - marvell,armada-380-smp
200              - marvell,armada-390-smp
201              - marvell,armada-xp-smp
202              - marvell,98dx3236-smp
203              - marvell,mmp3-smp
204              - mediatek,mt6589-smp
205              - mediatek,mt81xx-tz-smp
206              - qcom,gcc-msm8660
207              - qcom,kpss-acc-v1
208              - qcom,kpss-acc-v2
209              - renesas,apmu
210              - renesas,r9a06g032-smp
211              - rockchip,rk3036-smp
212              - rockchip,rk3066-smp
213              - socionext,milbeaut-m10v-smp
214              - ste,dbx500-smp
215
216  cpu-release-addr:
217    $ref: '/schemas/types.yaml#/definitions/uint64'
218
219    description:
220      Required for systems that have an "enable-method"
221        property value of "spin-table".
222      On ARM v8 64-bit systems must be a two cell
223        property identifying a 64-bit zero-initialised
224        memory location.
225
226  cpu-idle-states:
227    $ref: '/schemas/types.yaml#/definitions/phandle-array'
228    description: |
229      List of phandles to idle state nodes supported
230      by this cpu (see ./idle-states.yaml).
231
232  capacity-dmips-mhz:
233    $ref: '/schemas/types.yaml#/definitions/uint32'
234    description:
235      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
236      DMIPS/MHz, relative to highest capacity-dmips-mhz
237      in the system.
238
239  dynamic-power-coefficient:
240    $ref: '/schemas/types.yaml#/definitions/uint32'
241    description:
242      A u32 value that represents the running time dynamic
243      power coefficient in units of uW/MHz/V^2. The
244      coefficient can either be calculated from power
245      measurements or derived by analysis.
246
247      The dynamic power consumption of the CPU  is
248      proportional to the square of the Voltage (V) and
249      the clock frequency (f). The coefficient is used to
250      calculate the dynamic power as below -
251
252      Pdyn = dynamic-power-coefficient * V^2 * f
253
254      where voltage is in V, frequency is in MHz.
255
256  power-domains:
257    $ref: '/schemas/types.yaml#/definitions/phandle-array'
258    description:
259      List of phandles and PM domain specifiers, as defined by bindings of the
260      PM domain provider (see also ../power_domain.txt).
261
262  power-domain-names:
263    $ref: '/schemas/types.yaml#/definitions/string-array'
264    description:
265      A list of power domain name strings sorted in the same order as the
266      power-domains property.
267
268      For PSCI based platforms, the name corresponding to the index of the PSCI
269      PM domain provider, must be "psci".
270
271  qcom,saw:
272    $ref: '/schemas/types.yaml#/definitions/phandle'
273    description: |
274      Specifies the SAW* node associated with this CPU.
275
276      Required for systems that have an "enable-method" property
277      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
278
279      * arm/msm/qcom,saw2.txt
280
281  qcom,acc:
282    $ref: '/schemas/types.yaml#/definitions/phandle'
283    description: |
284      Specifies the ACC* node associated with this CPU.
285
286      Required for systems that have an "enable-method" property
287      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
288
289      * arm/msm/qcom,kpss-acc.txt
290
291  rockchip,pmu:
292    $ref: '/schemas/types.yaml#/definitions/phandle'
293    description: |
294      Specifies the syscon node controlling the cpu core power domains.
295
296      Optional for systems that have an "enable-method"
297      property value of "rockchip,rk3066-smp"
298      While optional, it is the preferred way to get access to
299      the cpu-core power-domains.
300
301required:
302  - device_type
303  - reg
304  - compatible
305
306dependencies:
307  rockchip,pmu: [enable-method]
308
309examples:
310  - |
311    cpus {
312      #size-cells = <0>;
313      #address-cells = <1>;
314
315      cpu@0 {
316        device_type = "cpu";
317        compatible = "arm,cortex-a15";
318        reg = <0x0>;
319      };
320
321      cpu@1 {
322        device_type = "cpu";
323        compatible = "arm,cortex-a15";
324        reg = <0x1>;
325      };
326
327      cpu@100 {
328        device_type = "cpu";
329        compatible = "arm,cortex-a7";
330        reg = <0x100>;
331      };
332
333      cpu@101 {
334        device_type = "cpu";
335        compatible = "arm,cortex-a7";
336        reg = <0x101>;
337      };
338    };
339
340  - |
341    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
342    cpus {
343      #size-cells = <0>;
344      #address-cells = <1>;
345
346      cpu@0 {
347        device_type = "cpu";
348        compatible = "arm,cortex-a8";
349        reg = <0x0>;
350      };
351    };
352
353  - |
354    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
355    cpus {
356      #size-cells = <0>;
357      #address-cells = <1>;
358
359      cpu@0 {
360        device_type = "cpu";
361        compatible = "arm,arm926ej-s";
362        reg = <0x0>;
363      };
364    };
365
366  - |
367    //  Example 4 (ARM Cortex-A57 64-bit system):
368    cpus {
369      #size-cells = <0>;
370      #address-cells = <2>;
371
372      cpu@0 {
373        device_type = "cpu";
374        compatible = "arm,cortex-a57";
375        reg = <0x0 0x0>;
376        enable-method = "spin-table";
377        cpu-release-addr = <0 0x20000000>;
378      };
379
380      cpu@1 {
381        device_type = "cpu";
382        compatible = "arm,cortex-a57";
383        reg = <0x0 0x1>;
384        enable-method = "spin-table";
385        cpu-release-addr = <0 0x20000000>;
386      };
387
388      cpu@100 {
389        device_type = "cpu";
390        compatible = "arm,cortex-a57";
391        reg = <0x0 0x100>;
392        enable-method = "spin-table";
393        cpu-release-addr = <0 0x20000000>;
394      };
395
396      cpu@101 {
397        device_type = "cpu";
398        compatible = "arm,cortex-a57";
399        reg = <0x0 0x101>;
400        enable-method = "spin-table";
401        cpu-release-addr = <0 0x20000000>;
402      };
403
404      cpu@10000 {
405        device_type = "cpu";
406        compatible = "arm,cortex-a57";
407        reg = <0x0 0x10000>;
408        enable-method = "spin-table";
409        cpu-release-addr = <0 0x20000000>;
410      };
411
412      cpu@10001 {
413        device_type = "cpu";
414        compatible = "arm,cortex-a57";
415        reg = <0x0 0x10001>;
416        enable-method = "spin-table";
417        cpu-release-addr = <0 0x20000000>;
418      };
419
420      cpu@10100 {
421        device_type = "cpu";
422        compatible = "arm,cortex-a57";
423        reg = <0x0 0x10100>;
424        enable-method = "spin-table";
425        cpu-release-addr = <0 0x20000000>;
426      };
427
428      cpu@10101 {
429        device_type = "cpu";
430        compatible = "arm,cortex-a57";
431        reg = <0x0 0x10101>;
432        enable-method = "spin-table";
433        cpu-release-addr = <0 0x20000000>;
434      };
435
436      cpu@100000000 {
437        device_type = "cpu";
438        compatible = "arm,cortex-a57";
439        reg = <0x1 0x0>;
440        enable-method = "spin-table";
441        cpu-release-addr = <0 0x20000000>;
442      };
443
444      cpu@100000001 {
445        device_type = "cpu";
446        compatible = "arm,cortex-a57";
447        reg = <0x1 0x1>;
448        enable-method = "spin-table";
449        cpu-release-addr = <0 0x20000000>;
450      };
451
452      cpu@100000100 {
453        device_type = "cpu";
454        compatible = "arm,cortex-a57";
455        reg = <0x1 0x100>;
456        enable-method = "spin-table";
457        cpu-release-addr = <0 0x20000000>;
458      };
459
460      cpu@100000101 {
461        device_type = "cpu";
462        compatible = "arm,cortex-a57";
463        reg = <0x1 0x101>;
464        enable-method = "spin-table";
465        cpu-release-addr = <0 0x20000000>;
466      };
467
468      cpu@100010000 {
469        device_type = "cpu";
470        compatible = "arm,cortex-a57";
471        reg = <0x1 0x10000>;
472        enable-method = "spin-table";
473        cpu-release-addr = <0 0x20000000>;
474      };
475
476      cpu@100010001 {
477        device_type = "cpu";
478        compatible = "arm,cortex-a57";
479        reg = <0x1 0x10001>;
480        enable-method = "spin-table";
481        cpu-release-addr = <0 0x20000000>;
482      };
483
484      cpu@100010100 {
485        device_type = "cpu";
486        compatible = "arm,cortex-a57";
487        reg = <0x1 0x10100>;
488        enable-method = "spin-table";
489        cpu-release-addr = <0 0x20000000>;
490      };
491
492      cpu@100010101 {
493        device_type = "cpu";
494        compatible = "arm,cortex-a57";
495        reg = <0x1 0x10101>;
496        enable-method = "spin-table";
497        cpu-release-addr = <0 0x20000000>;
498      };
499    };
500...
501