1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-a78
141      - arm,cortex-a510
142      - arm,cortex-a710
143      - arm,cortex-m0
144      - arm,cortex-m0+
145      - arm,cortex-m1
146      - arm,cortex-m3
147      - arm,cortex-m4
148      - arm,cortex-r4
149      - arm,cortex-r5
150      - arm,cortex-r7
151      - arm,cortex-x1
152      - arm,cortex-x2
153      - arm,neoverse-e1
154      - arm,neoverse-n1
155      - arm,neoverse-n2
156      - arm,neoverse-v1
157      - brcm,brahma-b15
158      - brcm,brahma-b53
159      - brcm,vulcan
160      - cavium,thunder
161      - cavium,thunder2
162      - faraday,fa526
163      - intel,sa110
164      - intel,sa1100
165      - marvell,feroceon
166      - marvell,mohawk
167      - marvell,pj4a
168      - marvell,pj4b
169      - marvell,sheeva-v5
170      - marvell,sheeva-v7
171      - nvidia,tegra132-denver
172      - nvidia,tegra186-denver
173      - nvidia,tegra194-carmel
174      - qcom,krait
175      - qcom,kryo
176      - qcom,kryo250
177      - qcom,kryo260
178      - qcom,kryo280
179      - qcom,kryo385
180      - qcom,kryo468
181      - qcom,kryo485
182      - qcom,kryo560
183      - qcom,kryo570
184      - qcom,kryo685
185      - qcom,kryo780
186      - qcom,scorpion
187
188  enable-method:
189    $ref: '/schemas/types.yaml#/definitions/string'
190    oneOf:
191      # On ARM v8 64-bit this property is required
192      - enum:
193          - psci
194          - spin-table
195      # On ARM 32-bit systems this property is optional
196      - enum:
197          - actions,s500-smp
198          - allwinner,sun6i-a31
199          - allwinner,sun8i-a23
200          - allwinner,sun9i-a80-smp
201          - allwinner,sun8i-a83t-smp
202          - amlogic,meson8-smp
203          - amlogic,meson8b-smp
204          - arm,realview-smp
205          - aspeed,ast2600-smp
206          - brcm,bcm11351-cpu-method
207          - brcm,bcm23550
208          - brcm,bcm2836-smp
209          - brcm,bcm63138
210          - brcm,bcm-nsp-smp
211          - brcm,brahma-b15
212          - marvell,armada-375-smp
213          - marvell,armada-380-smp
214          - marvell,armada-390-smp
215          - marvell,armada-xp-smp
216          - marvell,98dx3236-smp
217          - marvell,mmp3-smp
218          - mediatek,mt6589-smp
219          - mediatek,mt81xx-tz-smp
220          - qcom,gcc-msm8660
221          - qcom,kpss-acc-v1
222          - qcom,kpss-acc-v2
223          - qcom,msm8226-smp
224          - qcom,msm8909-smp
225          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
226          - qcom,msm8916-smp
227          - renesas,apmu
228          - renesas,r9a06g032-smp
229          - rockchip,rk3036-smp
230          - rockchip,rk3066-smp
231          - socionext,milbeaut-m10v-smp
232          - ste,dbx500-smp
233          - ti,am3352
234          - ti,am4372
235
236  cpu-release-addr:
237    oneOf:
238      - $ref: '/schemas/types.yaml#/definitions/uint32'
239      - $ref: '/schemas/types.yaml#/definitions/uint64'
240    description:
241      The DT specification defines this as 64-bit always, but some 32-bit Arm
242      systems have used a 32-bit value which must be supported.
243      Required for systems that have an "enable-method"
244        property value of "spin-table".
245
246  cpu-idle-states:
247    $ref: '/schemas/types.yaml#/definitions/phandle-array'
248    items:
249      maxItems: 1
250    description: |
251      List of phandles to idle state nodes supported
252      by this cpu (see ./idle-states.yaml).
253
254  capacity-dmips-mhz:
255    description:
256      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
257      DMIPS/MHz, relative to highest capacity-dmips-mhz
258      in the system.
259
260  cci-control-port: true
261
262  dynamic-power-coefficient:
263    $ref: '/schemas/types.yaml#/definitions/uint32'
264    description:
265      A u32 value that represents the running time dynamic
266      power coefficient in units of uW/MHz/V^2. The
267      coefficient can either be calculated from power
268      measurements or derived by analysis.
269
270      The dynamic power consumption of the CPU  is
271      proportional to the square of the Voltage (V) and
272      the clock frequency (f). The coefficient is used to
273      calculate the dynamic power as below -
274
275      Pdyn = dynamic-power-coefficient * V^2 * f
276
277      where voltage is in V, frequency is in MHz.
278
279  performance-domains:
280    maxItems: 1
281    description:
282      List of phandles and performance domain specifiers, as defined by
283      bindings of the performance domain provider. See also
284      dvfs/performance-domain.yaml.
285
286  power-domains:
287    description:
288      List of phandles and PM domain specifiers, as defined by bindings of the
289      PM domain provider (see also ../power_domain.txt).
290
291  power-domain-names:
292    description:
293      A list of power domain name strings sorted in the same order as the
294      power-domains property.
295
296      For PSCI based platforms, the name corresponding to the index of the PSCI
297      PM domain provider, must be "psci".
298
299  qcom,saw:
300    $ref: '/schemas/types.yaml#/definitions/phandle'
301    description: |
302      Specifies the SAW* node associated with this CPU.
303
304      Required for systems that have an "enable-method" property
305      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
306
307      * arm/msm/qcom,saw2.txt
308
309  qcom,acc:
310    $ref: '/schemas/types.yaml#/definitions/phandle'
311    description: |
312      Specifies the ACC* node associated with this CPU.
313
314      Required for systems that have an "enable-method" property
315      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
316      "qcom,msm8916-smp".
317
318      * arm/msm/qcom,kpss-acc.txt
319
320  rockchip,pmu:
321    $ref: '/schemas/types.yaml#/definitions/phandle'
322    description: |
323      Specifies the syscon node controlling the cpu core power domains.
324
325      Optional for systems that have an "enable-method"
326      property value of "rockchip,rk3066-smp"
327      While optional, it is the preferred way to get access to
328      the cpu-core power-domains.
329
330  secondary-boot-reg:
331    $ref: '/schemas/types.yaml#/definitions/uint32'
332    description: |
333      Required for systems that have an "enable-method" property value of
334      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
335
336      This includes the following SoCs: |
337      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
338      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
339
340      The secondary-boot-reg property is a u32 value that specifies the
341      physical address of the register used to request the ROM holding pen
342      code release a secondary CPU. The value written to the register is
343      formed by encoding the target CPU id into the low bits of the
344      physical start address it should jump to.
345
346if:
347  # If the enable-method property contains one of those values
348  properties:
349    enable-method:
350      contains:
351        enum:
352          - brcm,bcm11351-cpu-method
353          - brcm,bcm23550
354          - brcm,bcm-nsp-smp
355  # and if enable-method is present
356  required:
357    - enable-method
358
359then:
360  required:
361    - secondary-boot-reg
362
363required:
364  - device_type
365  - reg
366  - compatible
367
368dependencies:
369  rockchip,pmu: [enable-method]
370
371additionalProperties: true
372
373examples:
374  - |
375    cpus {
376      #size-cells = <0>;
377      #address-cells = <1>;
378
379      cpu@0 {
380        device_type = "cpu";
381        compatible = "arm,cortex-a15";
382        reg = <0x0>;
383      };
384
385      cpu@1 {
386        device_type = "cpu";
387        compatible = "arm,cortex-a15";
388        reg = <0x1>;
389      };
390
391      cpu@100 {
392        device_type = "cpu";
393        compatible = "arm,cortex-a7";
394        reg = <0x100>;
395      };
396
397      cpu@101 {
398        device_type = "cpu";
399        compatible = "arm,cortex-a7";
400        reg = <0x101>;
401      };
402    };
403
404  - |
405    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
406    cpus {
407      #size-cells = <0>;
408      #address-cells = <1>;
409
410      cpu@0 {
411        device_type = "cpu";
412        compatible = "arm,cortex-a8";
413        reg = <0x0>;
414      };
415    };
416
417  - |
418    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
419    cpus {
420      #size-cells = <0>;
421      #address-cells = <1>;
422
423      cpu@0 {
424        device_type = "cpu";
425        compatible = "arm,arm926ej-s";
426        reg = <0x0>;
427      };
428    };
429
430  - |
431    //  Example 4 (ARM Cortex-A57 64-bit system):
432    cpus {
433      #size-cells = <0>;
434      #address-cells = <2>;
435
436      cpu@0 {
437        device_type = "cpu";
438        compatible = "arm,cortex-a57";
439        reg = <0x0 0x0>;
440        enable-method = "spin-table";
441        cpu-release-addr = <0 0x20000000>;
442      };
443
444      cpu@1 {
445        device_type = "cpu";
446        compatible = "arm,cortex-a57";
447        reg = <0x0 0x1>;
448        enable-method = "spin-table";
449        cpu-release-addr = <0 0x20000000>;
450      };
451
452      cpu@100 {
453        device_type = "cpu";
454        compatible = "arm,cortex-a57";
455        reg = <0x0 0x100>;
456        enable-method = "spin-table";
457        cpu-release-addr = <0 0x20000000>;
458      };
459
460      cpu@101 {
461        device_type = "cpu";
462        compatible = "arm,cortex-a57";
463        reg = <0x0 0x101>;
464        enable-method = "spin-table";
465        cpu-release-addr = <0 0x20000000>;
466      };
467
468      cpu@10000 {
469        device_type = "cpu";
470        compatible = "arm,cortex-a57";
471        reg = <0x0 0x10000>;
472        enable-method = "spin-table";
473        cpu-release-addr = <0 0x20000000>;
474      };
475
476      cpu@10001 {
477        device_type = "cpu";
478        compatible = "arm,cortex-a57";
479        reg = <0x0 0x10001>;
480        enable-method = "spin-table";
481        cpu-release-addr = <0 0x20000000>;
482      };
483
484      cpu@10100 {
485        device_type = "cpu";
486        compatible = "arm,cortex-a57";
487        reg = <0x0 0x10100>;
488        enable-method = "spin-table";
489        cpu-release-addr = <0 0x20000000>;
490      };
491
492      cpu@10101 {
493        device_type = "cpu";
494        compatible = "arm,cortex-a57";
495        reg = <0x0 0x10101>;
496        enable-method = "spin-table";
497        cpu-release-addr = <0 0x20000000>;
498      };
499
500      cpu@100000000 {
501        device_type = "cpu";
502        compatible = "arm,cortex-a57";
503        reg = <0x1 0x0>;
504        enable-method = "spin-table";
505        cpu-release-addr = <0 0x20000000>;
506      };
507
508      cpu@100000001 {
509        device_type = "cpu";
510        compatible = "arm,cortex-a57";
511        reg = <0x1 0x1>;
512        enable-method = "spin-table";
513        cpu-release-addr = <0 0x20000000>;
514      };
515
516      cpu@100000100 {
517        device_type = "cpu";
518        compatible = "arm,cortex-a57";
519        reg = <0x1 0x100>;
520        enable-method = "spin-table";
521        cpu-release-addr = <0 0x20000000>;
522      };
523
524      cpu@100000101 {
525        device_type = "cpu";
526        compatible = "arm,cortex-a57";
527        reg = <0x1 0x101>;
528        enable-method = "spin-table";
529        cpu-release-addr = <0 0x20000000>;
530      };
531
532      cpu@100010000 {
533        device_type = "cpu";
534        compatible = "arm,cortex-a57";
535        reg = <0x1 0x10000>;
536        enable-method = "spin-table";
537        cpu-release-addr = <0 0x20000000>;
538      };
539
540      cpu@100010001 {
541        device_type = "cpu";
542        compatible = "arm,cortex-a57";
543        reg = <0x1 0x10001>;
544        enable-method = "spin-table";
545        cpu-release-addr = <0 0x20000000>;
546      };
547
548      cpu@100010100 {
549        device_type = "cpu";
550        compatible = "arm,cortex-a57";
551        reg = <0x1 0x10100>;
552        enable-method = "spin-table";
553        cpu-release-addr = <0 0x20000000>;
554      };
555
556      cpu@100010101 {
557        device_type = "cpu";
558        compatible = "arm,cortex-a57";
559        reg = <0x1 0x10101>;
560        enable-method = "spin-table";
561        cpu-release-addr = <0 0x20000000>;
562      };
563    };
564...
565