1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs bindings 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 $nodename: 43 const: cpus 44 description: Container of cpu nodes 45 46 '#address-cells': 47 enum: [1, 2] 48 description: | 49 Definition depends on ARM architecture version and configuration: 50 51 On uniprocessor ARM architectures previous to v7 52 value must be 1, to enable a simple enumeration 53 scheme for processors that do not have a HW CPU 54 identification register. 55 On 32-bit ARM 11 MPcore, ARM v7 or later systems 56 value must be 1, that corresponds to CPUID/MPIDR 57 registers sizes. 58 On ARM v8 64-bit systems value should be set to 2, 59 that corresponds to the MPIDR_EL1 register size. 60 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 61 in the system, #address-cells can be set to 1, since 62 MPIDR_EL1[63:32] bits are not used for CPUs 63 identification. 64 65 '#size-cells': 66 const: 0 67 68patternProperties: 69 '^cpu@[0-9a-f]+$': 70 properties: 71 device_type: 72 const: cpu 73 74 reg: 75 maxItems: 1 76 description: | 77 Usage and definition depend on ARM architecture version and 78 configuration: 79 80 On uniprocessor ARM architectures previous to v7 81 this property is required and must be set to 0. 82 83 On ARM 11 MPcore based systems this property is 84 required and matches the CPUID[11:0] register bits. 85 86 Bits [11:0] in the reg cell must be set to 87 bits [11:0] in CPU ID register. 88 89 All other bits in the reg cell must be set to 0. 90 91 On 32-bit ARM v7 or later systems this property is 92 required and matches the CPU MPIDR[23:0] register 93 bits. 94 95 Bits [23:0] in the reg cell must be set to 96 bits [23:0] in MPIDR. 97 98 All other bits in the reg cell must be set to 0. 99 100 On ARM v8 64-bit systems this property is required 101 and matches the MPIDR_EL1 register affinity bits. 102 103 * If cpus node's #address-cells property is set to 2 104 105 The first reg cell bits [7:0] must be set to 106 bits [39:32] of MPIDR_EL1. 107 108 The second reg cell bits [23:0] must be set to 109 bits [23:0] of MPIDR_EL1. 110 111 * If cpus node's #address-cells property is set to 1 112 113 The reg cell bits [23:0] must be set to bits [23:0] 114 of MPIDR_EL1. 115 116 All other bits in the reg cells must be set to 0. 117 118 compatible: 119 items: 120 - enum: 121 - arm,arm710t 122 - arm,arm720t 123 - arm,arm740t 124 - arm,arm7ej-s 125 - arm,arm7tdmi 126 - arm,arm7tdmi-s 127 - arm,arm9es 128 - arm,arm9ej-s 129 - arm,arm920t 130 - arm,arm922t 131 - arm,arm925 132 - arm,arm926e-s 133 - arm,arm926ej-s 134 - arm,arm940t 135 - arm,arm946e-s 136 - arm,arm966e-s 137 - arm,arm968e-s 138 - arm,arm9tdmi 139 - arm,arm1020e 140 - arm,arm1020t 141 - arm,arm1022e 142 - arm,arm1026ej-s 143 - arm,arm1136j-s 144 - arm,arm1136jf-s 145 - arm,arm1156t2-s 146 - arm,arm1156t2f-s 147 - arm,arm1176jzf 148 - arm,arm1176jz-s 149 - arm,arm1176jzf-s 150 - arm,arm11mpcore 151 - arm,armv8 # Only for s/w models 152 - arm,cortex-a5 153 - arm,cortex-a7 154 - arm,cortex-a8 155 - arm,cortex-a9 156 - arm,cortex-a12 157 - arm,cortex-a15 158 - arm,cortex-a17 159 - arm,cortex-a53 160 - arm,cortex-a57 161 - arm,cortex-a72 162 - arm,cortex-a73 163 - arm,cortex-m0 164 - arm,cortex-m0+ 165 - arm,cortex-m1 166 - arm,cortex-m3 167 - arm,cortex-m4 168 - arm,cortex-r4 169 - arm,cortex-r5 170 - arm,cortex-r7 171 - brcm,brahma-b15 172 - brcm,brahma-b53 173 - brcm,vulcan 174 - cavium,thunder 175 - cavium,thunder2 176 - faraday,fa526 177 - intel,sa110 178 - intel,sa1100 179 - marvell,feroceon 180 - marvell,mohawk 181 - marvell,pj4a 182 - marvell,pj4b 183 - marvell,sheeva-v5 184 - marvell,sheeva-v7 185 - nvidia,tegra132-denver 186 - nvidia,tegra186-denver 187 - nvidia,tegra194-carmel 188 - qcom,krait 189 - qcom,kryo 190 - qcom,kryo385 191 - qcom,scorpion 192 193 enable-method: 194 allOf: 195 - $ref: '/schemas/types.yaml#/definitions/string' 196 - oneOf: 197 # On ARM v8 64-bit this property is required 198 - enum: 199 - psci 200 - spin-table 201 # On ARM 32-bit systems this property is optional 202 - enum: 203 - actions,s500-smp 204 - allwinner,sun6i-a31 205 - allwinner,sun8i-a23 206 - allwinner,sun9i-a80-smp 207 - allwinner,sun8i-a83t-smp 208 - amlogic,meson8-smp 209 - amlogic,meson8b-smp 210 - arm,realview-smp 211 - brcm,bcm11351-cpu-method 212 - brcm,bcm23550 213 - brcm,bcm2836-smp 214 - brcm,bcm63138 215 - brcm,bcm-nsp-smp 216 - brcm,brahma-b15 217 - marvell,armada-375-smp 218 - marvell,armada-380-smp 219 - marvell,armada-390-smp 220 - marvell,armada-xp-smp 221 - marvell,98dx3236-smp 222 - mediatek,mt6589-smp 223 - mediatek,mt81xx-tz-smp 224 - qcom,gcc-msm8660 225 - qcom,kpss-acc-v1 226 - qcom,kpss-acc-v2 227 - renesas,apmu 228 - renesas,r9a06g032-smp 229 - rockchip,rk3036-smp 230 - rockchip,rk3066-smp 231 - socionext,milbeaut-m10v-smp 232 - ste,dbx500-smp 233 234 cpu-release-addr: 235 $ref: '/schemas/types.yaml#/definitions/uint64' 236 237 description: 238 Required for systems that have an "enable-method" 239 property value of "spin-table". 240 On ARM v8 64-bit systems must be a two cell 241 property identifying a 64-bit zero-initialised 242 memory location. 243 244 cpu-idle-states: 245 $ref: '/schemas/types.yaml#/definitions/phandle-array' 246 description: | 247 List of phandles to idle state nodes supported 248 by this cpu (see ./idle-states.txt). 249 250 capacity-dmips-mhz: 251 $ref: '/schemas/types.yaml#/definitions/uint32' 252 description: 253 u32 value representing CPU capacity (see ./cpu-capacity.txt) in 254 DMIPS/MHz, relative to highest capacity-dmips-mhz 255 in the system. 256 257 dynamic-power-coefficient: 258 $ref: '/schemas/types.yaml#/definitions/uint32' 259 description: 260 A u32 value that represents the running time dynamic 261 power coefficient in units of uW/MHz/V^2. The 262 coefficient can either be calculated from power 263 measurements or derived by analysis. 264 265 The dynamic power consumption of the CPU is 266 proportional to the square of the Voltage (V) and 267 the clock frequency (f). The coefficient is used to 268 calculate the dynamic power as below - 269 270 Pdyn = dynamic-power-coefficient * V^2 * f 271 272 where voltage is in V, frequency is in MHz. 273 274 qcom,saw: 275 $ref: '/schemas/types.yaml#/definitions/phandle' 276 description: | 277 Specifies the SAW* node associated with this CPU. 278 279 Required for systems that have an "enable-method" property 280 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 281 282 * arm/msm/qcom,saw2.txt 283 284 qcom,acc: 285 $ref: '/schemas/types.yaml#/definitions/phandle' 286 description: | 287 Specifies the ACC* node associated with this CPU. 288 289 Required for systems that have an "enable-method" property 290 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 291 292 * arm/msm/qcom,kpss-acc.txt 293 294 rockchip,pmu: 295 $ref: '/schemas/types.yaml#/definitions/phandle' 296 description: | 297 Specifies the syscon node controlling the cpu core power domains. 298 299 Optional for systems that have an "enable-method" 300 property value of "rockchip,rk3066-smp" 301 While optional, it is the preferred way to get access to 302 the cpu-core power-domains. 303 304 required: 305 - device_type 306 - reg 307 - compatible 308 309 dependencies: 310 cpu-release-addr: [enable-method] 311 rockchip,pmu: [enable-method] 312 313required: 314 - '#address-cells' 315 - '#size-cells' 316 317examples: 318 - | 319 cpus { 320 #size-cells = <0>; 321 #address-cells = <1>; 322 323 cpu@0 { 324 device_type = "cpu"; 325 compatible = "arm,cortex-a15"; 326 reg = <0x0>; 327 }; 328 329 cpu@1 { 330 device_type = "cpu"; 331 compatible = "arm,cortex-a15"; 332 reg = <0x1>; 333 }; 334 335 cpu@100 { 336 device_type = "cpu"; 337 compatible = "arm,cortex-a7"; 338 reg = <0x100>; 339 }; 340 341 cpu@101 { 342 device_type = "cpu"; 343 compatible = "arm,cortex-a7"; 344 reg = <0x101>; 345 }; 346 }; 347 348 - | 349 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 350 cpus { 351 #size-cells = <0>; 352 #address-cells = <1>; 353 354 cpu@0 { 355 device_type = "cpu"; 356 compatible = "arm,cortex-a8"; 357 reg = <0x0>; 358 }; 359 }; 360 361 - | 362 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 363 cpus { 364 #size-cells = <0>; 365 #address-cells = <1>; 366 367 cpu@0 { 368 device_type = "cpu"; 369 compatible = "arm,arm926ej-s"; 370 reg = <0x0>; 371 }; 372 }; 373 374 - | 375 // Example 4 (ARM Cortex-A57 64-bit system): 376 cpus { 377 #size-cells = <0>; 378 #address-cells = <2>; 379 380 cpu@0 { 381 device_type = "cpu"; 382 compatible = "arm,cortex-a57"; 383 reg = <0x0 0x0>; 384 enable-method = "spin-table"; 385 cpu-release-addr = <0 0x20000000>; 386 }; 387 388 cpu@1 { 389 device_type = "cpu"; 390 compatible = "arm,cortex-a57"; 391 reg = <0x0 0x1>; 392 enable-method = "spin-table"; 393 cpu-release-addr = <0 0x20000000>; 394 }; 395 396 cpu@100 { 397 device_type = "cpu"; 398 compatible = "arm,cortex-a57"; 399 reg = <0x0 0x100>; 400 enable-method = "spin-table"; 401 cpu-release-addr = <0 0x20000000>; 402 }; 403 404 cpu@101 { 405 device_type = "cpu"; 406 compatible = "arm,cortex-a57"; 407 reg = <0x0 0x101>; 408 enable-method = "spin-table"; 409 cpu-release-addr = <0 0x20000000>; 410 }; 411 412 cpu@10000 { 413 device_type = "cpu"; 414 compatible = "arm,cortex-a57"; 415 reg = <0x0 0x10000>; 416 enable-method = "spin-table"; 417 cpu-release-addr = <0 0x20000000>; 418 }; 419 420 cpu@10001 { 421 device_type = "cpu"; 422 compatible = "arm,cortex-a57"; 423 reg = <0x0 0x10001>; 424 enable-method = "spin-table"; 425 cpu-release-addr = <0 0x20000000>; 426 }; 427 428 cpu@10100 { 429 device_type = "cpu"; 430 compatible = "arm,cortex-a57"; 431 reg = <0x0 0x10100>; 432 enable-method = "spin-table"; 433 cpu-release-addr = <0 0x20000000>; 434 }; 435 436 cpu@10101 { 437 device_type = "cpu"; 438 compatible = "arm,cortex-a57"; 439 reg = <0x0 0x10101>; 440 enable-method = "spin-table"; 441 cpu-release-addr = <0 0x20000000>; 442 }; 443 444 cpu@100000000 { 445 device_type = "cpu"; 446 compatible = "arm,cortex-a57"; 447 reg = <0x1 0x0>; 448 enable-method = "spin-table"; 449 cpu-release-addr = <0 0x20000000>; 450 }; 451 452 cpu@100000001 { 453 device_type = "cpu"; 454 compatible = "arm,cortex-a57"; 455 reg = <0x1 0x1>; 456 enable-method = "spin-table"; 457 cpu-release-addr = <0 0x20000000>; 458 }; 459 460 cpu@100000100 { 461 device_type = "cpu"; 462 compatible = "arm,cortex-a57"; 463 reg = <0x1 0x100>; 464 enable-method = "spin-table"; 465 cpu-release-addr = <0 0x20000000>; 466 }; 467 468 cpu@100000101 { 469 device_type = "cpu"; 470 compatible = "arm,cortex-a57"; 471 reg = <0x1 0x101>; 472 enable-method = "spin-table"; 473 cpu-release-addr = <0 0x20000000>; 474 }; 475 476 cpu@100010000 { 477 device_type = "cpu"; 478 compatible = "arm,cortex-a57"; 479 reg = <0x1 0x10000>; 480 enable-method = "spin-table"; 481 cpu-release-addr = <0 0x20000000>; 482 }; 483 484 cpu@100010001 { 485 device_type = "cpu"; 486 compatible = "arm,cortex-a57"; 487 reg = <0x1 0x10001>; 488 enable-method = "spin-table"; 489 cpu-release-addr = <0 0x20000000>; 490 }; 491 492 cpu@100010100 { 493 device_type = "cpu"; 494 compatible = "arm,cortex-a57"; 495 reg = <0x1 0x10100>; 496 enable-method = "spin-table"; 497 cpu-release-addr = <0 0x20000000>; 498 }; 499 500 cpu@100010101 { 501 device_type = "cpu"; 502 compatible = "arm,cortex-a57"; 503 reg = <0x1 0x10101>; 504 enable-method = "spin-table"; 505 cpu-release-addr = <0 0x20000000>; 506 }; 507 }; 508... 509