1ARM Broadcom STB platforms Device Tree Bindings
2-----------------------------------------------
3Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
4SoC shall have the following DT organization:
5
6Required root node properties:
7    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
8
9example:
10/ {
11    #address-cells = <2>;
12    #size-cells = <2>;
13    model = "Broadcom STB (bcm7445)";
14    compatible = "brcm,bcm7445", "brcm,brcmstb";
15
16Further, syscon nodes that map platform-specific registers used for general
17system control is required:
18
19    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
21    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
22
23hif-cpubiuctrl node
24-------------------
25SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
26(BIU) block which controls and interfaces the CPU complex to the different
27Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
28offers a feature called Write Pairing which consists in collapsing two adjacent
29cache lines into a single (bursted) write transaction towards the memory
30controller (MEMC) to maximize write bandwidth.
31
32Required properties:
33
34    - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
35
36Optional properties:
37
38    - brcm,write-pairing:
39	Boolean property, which when present indicates that the chip
40	supports write-pairing.
41
42example:
43    rdb {
44        #address-cells = <1>;
45        #size-cells = <1>;
46        compatible = "simple-bus";
47        ranges = <0 0x00 0xf0000000 0x1000000>;
48
49        sun_top_ctrl: syscon@404000 {
50            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
51            reg = <0x404000 0x51c>;
52        };
53
54        hif_cpubiuctrl: syscon@3e2400 {
55            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
56            reg = <0x3e2400 0x5b4>;
57            brcm,write-pairing;
58        };
59
60        hif_continuation: syscon@452000 {
61            compatible = "brcm,bcm7445-hif-continuation", "syscon";
62            reg = <0x452000 0x100>;
63        };
64    };
65
66Nodes that allow for support of SMP initialization and reboot are required:
67
68smpboot
69-------
70Required properties:
71
72    - compatible
73        The string "brcm,brcmstb-smpboot".
74
75    - syscon-cpu
76        A phandle / integer array property which lets the BSP know the location
77        of certain CPU power-on registers.
78
79        The layout of the property is as follows:
80            o a phandle to the "hif_cpubiuctrl" syscon node
81            o offset to the base CPU power zone register
82            o offset to the base CPU reset register
83
84    - syscon-cont
85        A phandle pointing to the syscon node which describes the CPU boot
86        continuation registers.
87            o a phandle to the "hif_continuation" syscon node
88
89example:
90    smpboot {
91        compatible = "brcm,brcmstb-smpboot";
92        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
93        syscon-cont = <&hif_continuation>;
94    };
95
96reboot
97-------
98Required properties
99
100    - compatible
101        The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
102        the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
103        chips with the old SUN_TOP_CTRL interface.
104
105    - syscon
106        A phandle / integer array that points to the syscon node which describes
107        the general system reset registers.
108            o a phandle to "sun_top_ctrl"
109            o offset to the "reset source enable" register
110            o offset to the "software master reset" register
111
112example:
113    reboot {
114        compatible = "brcm,brcmstb-reboot";
115        syscon = <&sun_top_ctrl 0x304 0x308>;
116    };
117
118
119
120Power management
121----------------
122
123For power management (particularly, S2/S3/S5 system suspend), the following SoC
124components are needed:
125
126= Always-On control block (AON CTRL)
127
128This hardware provides control registers for the "always-on" (even in low-power
129modes) hardware, such as the Power Management State Machine (PMSM).
130
131Required properties:
132- compatible     : should contain "brcm,brcmstb-aon-ctrl"
133- reg            : the register start and length for the AON CTRL block
134
135Example:
136
137aon-ctrl@410000 {
138	compatible = "brcm,brcmstb-aon-ctrl";
139	reg = <0x410000 0x400>;
140};
141
142= Memory controllers
143
144A Broadcom STB SoC typically has a number of independent memory controllers,
145each of which may have several associated hardware blocks, which are versioned
146independently (control registers, DDR PHYs, etc.). One might consider
147describing these controllers as a parent "memory controllers" block, which
148contains N sub-nodes (one for each controller in the system), each of which is
149associated with a number of hardware register resources (e.g., its PHY). See
150the example device tree snippet below.
151
152== MEMC (MEMory Controller)
153
154Represents a single memory controller instance.
155
156Required properties:
157- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
158
159Should contain subnodes for any of the following relevant hardware resources:
160
161== DDR PHY control
162
163Control registers for this memory controller's DDR PHY.
164
165Required properties:
166- compatible     : should contain one of these
167	"brcm,brcmstb-ddr-phy-v225.1"
168	"brcm,brcmstb-ddr-phy-v240.1"
169	"brcm,brcmstb-ddr-phy-v240.2"
170
171- reg            : the DDR PHY register range
172
173== DDR SHIMPHY
174
175Control registers for this memory controller's DDR SHIMPHY.
176
177Required properties:
178- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
179- reg            : the DDR SHIMPHY register range
180
181== MEMC DDR control
182
183Sequencer DRAM parameters and control registers. Used for Self-Refresh
184Power-Down (SRPD), among other things.
185
186Required properties:
187- compatible     : should contain "brcm,brcmstb-memc-ddr"
188- reg            : the MEMC DDR register range
189
190Example:
191
192memory_controllers {
193	ranges;
194	compatible = "simple-bus";
195
196	memc@0 {
197		compatible = "brcm,brcmstb-memc", "simple-bus";
198		ranges;
199
200		ddr-phy@f1106000 {
201			compatible = "brcm,brcmstb-ddr-phy-v240.1";
202			reg = <0xf1106000 0x21c>;
203		};
204
205		shimphy@f1108000 {
206			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
207			reg = <0xf1108000 0xe4>;
208		};
209
210		memc-ddr@f1102000 {
211			reg = <0xf1102000 0x800>;
212			compatible = "brcm,brcmstb-memc-ddr";
213		};
214	};
215
216	memc@1 {
217		compatible = "brcm,brcmstb-memc", "simple-bus";
218		ranges;
219
220		ddr-phy@f1186000 {
221			compatible = "brcm,brcmstb-ddr-phy-v240.1";
222			reg = <0xf1186000 0x21c>;
223		};
224
225		shimphy@f1188000 {
226			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
227			reg = <0xf1188000 0xe4>;
228		};
229
230		memc-ddr@f1182000 {
231			reg = <0xf1182000 0x800>;
232			compatible = "brcm,brcmstb-memc-ddr";
233		};
234	};
235
236	memc@2 {
237		compatible = "brcm,brcmstb-memc", "simple-bus";
238		ranges;
239
240		ddr-phy@f1206000 {
241			compatible = "brcm,brcmstb-ddr-phy-v240.1";
242			reg = <0xf1206000 0x21c>;
243		};
244
245		shimphy@f1208000 {
246			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
247			reg = <0xf1208000 0xe4>;
248		};
249
250		memc-ddr@f1202000 {
251			reg = <0xf1202000 0x800>;
252			compatible = "brcm,brcmstb-memc-ddr";
253		};
254	};
255};
256