1Atmel system registers
2
3Chipid required properties:
4- compatible: Should be "atmel,sama5d2-chipid"
5- reg : Should contain registers location and length
6
7PIT Timer required properties:
8- compatible: Should be "atmel,at91sam9260-pit"
9- reg: Should contain registers location and length
10- interrupts: Should contain interrupt for the PIT which is the IRQ line
11  shared across all System Controller members.
12
13System Timer (ST) required properties:
14- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
15- reg: Should contain registers location and length
16- interrupts: Should contain interrupt for the ST which is the IRQ line
17  shared across all System Controller members.
18- clocks: phandle to input clock.
19Its subnodes can be:
20- watchdog: compatible should be "atmel,at91rm9200-wdt"
21
22RSTC Reset Controller required properties:
23- compatible: Should be "atmel,<chip>-rstc".
24  <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
25  it also can be "microchip,sam9x60-rstc"
26- reg: Should contain registers location and length
27- clocks: phandle to input clock.
28
29Example:
30
31	rstc@fffffd00 {
32		compatible = "atmel,at91sam9260-rstc";
33		reg = <0xfffffd00 0x10>;
34		clocks = <&clk32k>;
35	};
36
37RAMC SDRAM/DDR Controller required properties:
38- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
39			"atmel,at91sam9260-sdramc",
40			"atmel,at91sam9g45-ddramc",
41			"atmel,sama5d3-ddramc",
42- reg: Should contain registers location and length
43
44Examples:
45
46	ramc0: ramc@ffffe800 {
47		compatible = "atmel,at91sam9g45-ddramc";
48		reg = <0xffffe800 0x200>;
49	};
50
51SHDWC Shutdown Controller
52
53required properties:
54- compatible: Should be "atmel,<chip>-shdwc".
55  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
56- reg: Should contain registers location and length
57- clocks: phandle to input clock.
58
59optional properties:
60- atmel,wakeup-mode: String, operation mode of the wakeup mode.
61  Supported values are: "none", "high", "low", "any".
62- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
63
64optional at91sam9260 properties:
65- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
66
67optional at91sam9rl properties:
68- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
69- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
70
71optional at91sam9x5 properties:
72- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
73
74Example:
75
76	shdwc@fffffd10 {
77		compatible = "atmel,at91sam9260-shdwc";
78		reg = <0xfffffd10 0x10>;
79		clocks = <&clk32k>;
80	};
81
82SHDWC SAMA5D2-Compatible Shutdown Controller
83
841) shdwc node
85
86required properties:
87- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
88- reg: should contain registers location and length
89- clocks: phandle to input clock.
90- #address-cells: should be one. The cell is the wake-up input index.
91- #size-cells: should be zero.
92
93optional properties:
94
95- debounce-delay-us: minimum wake-up inputs debouncer period in
96  microseconds. It's usually a board-related property.
97- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
98
99optional microchip,sam9x60-shdwc properties:
100- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
101
102The node contains child nodes for each wake-up input that the platform uses.
103
1042) input nodes
105
106Wake-up input nodes are usually described in the "board" part of the Device
107Tree. Note also that input 0 is linked to the wake-up pin and is frequently
108used.
109
110Required properties:
111- reg: should contain the wake-up input index [0 - 15].
112
113Optional properties:
114- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
115  by the child, forces the wake-up of the core power supply on a high level.
116  The default is to be active low.
117
118Example:
119
120On the SoC side:
121	shdwc@f8048010 {
122		compatible = "atmel,sama5d2-shdwc";
123		reg = <0xf8048010 0x10>;
124		clocks = <&clk32k>;
125		#address-cells = <1>;
126		#size-cells = <0>;
127		atmel,wakeup-rtc-timer;
128	};
129
130On the board side:
131	shdwc@f8048010 {
132		debounce-delay-us = <976>;
133
134		input@0 {
135			reg = <0>;
136		};
137
138		input@1 {
139			reg = <1>;
140			atmel,wakeup-active-high;
141		};
142	};
143
144Special Function Registers (SFR)
145
146Special Function Registers (SFR) manage specific aspects of the integrated
147memory, bridge implementations, processor and other functionality not controlled
148elsewhere.
149
150required properties:
151- compatible: Should be "atmel,<chip>-sfr", "syscon" or
152	"atmel,<chip>-sfrbu", "syscon"
153  <chip> can be "sama5d3", "sama5d4" or "sama5d2".
154  It also can be "microchip,sam9x60-sfr", "syscon".
155- reg: Should contain registers location and length
156
157	sfr@f0038000 {
158		compatible = "atmel,sama5d3-sfr", "syscon";
159		reg = <0xf0038000 0x60>;
160	};
161
162Security Module (SECUMOD)
163
164The Security Module macrocell provides all necessary secure functions to avoid
165voltage, temperature, frequency and mechanical attacks on the chip. It also
166embeds secure memories that can be scrambled.
167
168The Security Module also offers the PIOBU pins which can be used as GPIO pins.
169Note that they maintain their voltage during Backup/Self-refresh.
170
171required properties:
172- compatible: Should be "atmel,<chip>-secumod", "syscon".
173  <chip> can be "sama5d2".
174- reg: Should contain registers location and length
175- gpio-controller:	Marks the port as GPIO controller.
176- #gpio-cells:		There are 2. The pin number is the
177			first, the second represents additional
178			parameters such as GPIO_ACTIVE_HIGH/LOW.
179
180
181	secumod@fc040000 {
182		compatible = "atmel,sama5d2-secumod", "syscon";
183		reg = <0xfc040000 0x100>;
184		gpio-controller;
185		#gpio-cells = <2>;
186	};
187