1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm CoreSight Embedded Trace MacroCell
8
9maintainers:
10  - Mathieu Poirier <mathieu.poirier@linaro.org>
11  - Mike Leach <mike.leach@linaro.org>
12  - Leo Yan <leo.yan@linaro.org>
13  - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15description: |
16  CoreSight components are compliant with the ARM CoreSight architecture
17  specification and can be connected in various topologies to suit a particular
18  SoCs tracing needs. These trace components can generally be classified as
19  sinks, links and sources. Trace data produced by one or more sources flows
20  through the intermediate links connecting the source to the currently selected
21  sink.
22
23  The Embedded Trace Macrocell (ETM) is a real-time trace module providing
24  instruction and data tracing of a processor.
25
26select:
27  properties:
28    compatible:
29      contains:
30        enum:
31          - arm,coresight-etm3x
32          - arm,coresight-etm4x
33          - arm,coresight-etm4x-sysreg
34  required:
35    - compatible
36
37allOf:
38  - if:
39      not:
40        properties:
41          compatible:
42            contains:
43              const: arm,coresight-etm4x-sysreg
44    then:
45      $ref: /schemas/arm/primecell.yaml#
46      required:
47        - reg
48
49properties:
50  compatible:
51    oneOf:
52      - description:
53          Embedded Trace Macrocell with memory mapped access.
54        items:
55          - enum:
56              - arm,coresight-etm3x
57              - arm,coresight-etm4x
58          - const: arm,primecell
59      - description:
60          Embedded Trace Macrocell (version 4.x), with system register access only
61        const: arm,coresight-etm4x-sysreg
62
63  reg:
64    maxItems: 1
65
66  clocks:
67    minItems: 1
68    maxItems: 2
69
70  clock-names:
71    minItems: 1
72    items:
73      - const: apb_pclk
74      - const: atclk
75
76  arm,coresight-loses-context-with-cpu:
77    type: boolean
78    description:
79      Indicates that the hardware will lose register context on CPU power down
80      (e.g. CPUIdle). An example of where this may be needed are systems which
81      contain a coresight component and CPU in the same power domain. When the
82      CPU powers down the coresight component also powers down and loses its
83      context.
84
85  arm,cp14:
86    type: boolean
87    description:
88      Must be present if the system accesses ETM/PTM management registers via
89      co-processor 14.
90
91  qcom,skip-power-up:
92    type: boolean
93    description:
94      Indicates that an implementation can skip powering up the trace unit.
95      TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
96      since ETMs are in the same power domain as their CPU cores. This property
97      is required to identify such systems with hardware errata where the CPU
98      watchdog counter is stopped when TRCPDCR.PU is set.
99
100  cpu:
101    description:
102      phandle to the cpu this ETM is bound to.
103    $ref: /schemas/types.yaml#/definitions/phandle
104
105  out-ports:
106    $ref: /schemas/graph.yaml#/properties/ports
107    additionalProperties: false
108
109    properties:
110      port:
111        description: Output connection from the ETM to CoreSight Trace bus.
112        $ref: /schemas/graph.yaml#/properties/port
113
114required:
115  - compatible
116  - clocks
117  - clock-names
118  - cpu
119  - out-ports
120
121unevaluatedProperties: false
122
123examples:
124  - |
125    ptm@2201c000 {
126        compatible = "arm,coresight-etm3x", "arm,primecell";
127        reg = <0x2201c000 0x1000>;
128
129        cpu = <&cpu0>;
130        clocks = <&oscclk6a>;
131        clock-names = "apb_pclk";
132        out-ports {
133            port {
134                ptm0_out_port: endpoint {
135                    remote-endpoint = <&funnel_in_port0>;
136                };
137            };
138        };
139    };
140
141    ptm@2201d000 {
142        compatible = "arm,coresight-etm3x", "arm,primecell";
143        reg = <0x2201d000 0x1000>;
144
145        cpu = <&cpu1>;
146        clocks = <&oscclk6a>;
147        clock-names = "apb_pclk";
148        out-ports {
149            port {
150                ptm1_out_port: endpoint {
151                    remote-endpoint = <&funnel_in_port1>;
152                };
153            };
154        };
155    };
156...
157