1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: ARM Coresight Cross Trigger Interface (CTI) device.
9
10description: |
11  The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12  to one or more CoreSight components and/or a CPU, with CTIs interconnected in
13  a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
14  The ECT components are not part of the trace generation data path and are thus
15  not part of the CoreSight graph.
16
17  The CTI component properties define the connections between the individual
18  CTI and the components it is directly connected to, consisting of input and
19  output hardware trigger signals. CTIs can have a maximum number of input and
20  output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
21  number is defined at design time, the maximum of each defined in the DEVID
22  register.
23
24  CTIs are interconnected in a star topology via the CTM, using a number of
25  programmable channels, usually 4, but again implementation defined and
26  described in the DEVID register. The star topology is not required to be
27  described in the bindings as the actual connections are software
28  programmable.
29
30  In general the connections between CTI and components via the trigger signals
31  are implementation defined, except when the CTI is connected to an ARM v8
32  architecture core and optional ETM.
33
34  In this case the ARM v8 architecture defines the required signal connections
35  between CTI and the CPU core and ETM if present. In the case of a v8
36  architecturally connected CTI an additional compatible string is used to
37  indicate this feature (arm,coresight-cti-v8-arch).
38
39  When CTI trigger connection information is unavailable then a minimal driver
40  binding can be declared with no explicit trigger signals. This will result
41  the driver detecting the maximum available triggers and channels from the
42  DEVID register and make them all available for use as a single default
43  connection. Any user / client application will require additional information
44  on the connections between the CTI and other components for correct operation.
45  This information might be found by enabling the Integration Test registers in
46  the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
47  configuration). These registers may be used to explore the trigger connections
48  between CTI and other CoreSight components.
49
50  Certain triggers between CoreSight devices and the CTI have specific types
51  and usages. These can be defined along with the signal indexes with the
52  constants defined in <dt-bindings/arm/coresight-cti-dt.h>
53
54  For example a CTI connected to a core will usually have a DBGREQ signal. This
55  is defined in the binding as type PE_EDBGREQ. These types will appear in an
56  optional array alongside the signal indexes. Omitting types will default all
57  signals to GEN_IO.
58
59  Note that some hardware trigger signals can be connected to non-CoreSight
60  components (e.g. UART etc) depending on hardware implementation.
61
62maintainers:
63  - Mike Leach <mike.leach@linaro.org>
64
65allOf:
66  - $ref: /schemas/arm/primecell.yaml#
67
68# Need a custom select here or 'arm,primecell' will match on lots of nodes
69select:
70  properties:
71    compatible:
72      contains:
73        enum:
74          - arm,coresight-cti
75  required:
76    - compatible
77
78properties:
79  $nodename:
80    pattern: "^cti(@[0-9a-f]+)$"
81  compatible:
82    oneOf:
83      - items:
84          - const: arm,coresight-cti
85          - const: arm,primecell
86      - items:
87          - const: arm,coresight-cti-v8-arch
88          - const: arm,coresight-cti
89          - const: arm,primecell
90
91  reg:
92    maxItems: 1
93
94  cpu:
95    $ref: /schemas/types.yaml#/definitions/phandle
96    description:
97      Handle to cpu this device is associated with. This must appear in the
98      base cti node if compatible string arm,coresight-cti-v8-arch is used,
99      or may appear in a trig-conns child node when appropriate.
100
101  arm,cti-ctm-id:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      Defines the CTM this CTI is connected to, in large systems with multiple
105      separate CTI/CTM nets. Typically multi-socket systems where the CTM is
106      propagated between sockets.
107
108  arm,cs-dev-assoc:
109    $ref: /schemas/types.yaml#/definitions/phandle
110    description:
111      defines a phandle reference to an associated CoreSight trace device.
112      When the associated trace device is enabled, then the respective CTI
113      will be enabled. Use in a trig-conns node, or in CTI base node when
114      compatible string arm,coresight-cti-v8-arch used. If the associated
115      device has not been registered then the node name will be stored as
116      the connection name for later resolution. If the associated device is
117      not a CoreSight device or not registered then the node name will remain
118      the connection name and automatic enabling will not occur.
119
120  # size cells and address cells required if trig-conns node present.
121  "#size-cells":
122    const: 0
123
124  "#address-cells":
125    const: 1
126
127patternProperties:
128  '^trig-conns@([0-9]+)$':
129    type: object
130    description:
131      A trigger connections child node which describes the trigger signals
132      between this CTI and another hardware device. This device may be a CPU,
133      CoreSight device, any other hardware device or simple external IO lines.
134      The connection may have both input and output triggers, or only one or the
135      other.
136
137    properties:
138      reg:
139        maxItems: 1
140
141      arm,trig-in-sigs:
142        $ref: /schemas/types.yaml#/definitions/uint32-array
143        minItems: 1
144        maxItems: 32
145        description:
146          List of CTI trigger in signal numbers in use by a trig-conns node.
147
148      arm,trig-in-types:
149        $ref: /schemas/types.yaml#/definitions/uint32-array
150        minItems: 1
151        maxItems: 32
152        description:
153          List of constants representing the types for the CTI trigger in
154          signals. Types in this array match to the corresponding signal in the
155          arm,trig-in-sigs array. If the -types array is smaller, or omitted
156          completely, then the types will default to GEN_IO.
157
158      arm,trig-out-sigs:
159        $ref: /schemas/types.yaml#/definitions/uint32-array
160        minItems: 1
161        maxItems: 32
162        description:
163          List of CTI trigger out signal numbers in use by a trig-conns node.
164
165      arm,trig-out-types:
166        $ref: /schemas/types.yaml#/definitions/uint32-array
167        minItems: 1
168        maxItems: 32
169        description:
170          List of constants representing the types for the CTI trigger out
171          signals. Types in this array match to the corresponding signal
172          in the arm,trig-out-sigs array. If the "-types" array is smaller,
173          or omitted completely, then the types will default to GEN_IO.
174
175      arm,trig-filters:
176        $ref: /schemas/types.yaml#/definitions/uint32-array
177        minItems: 1
178        maxItems: 32
179        description:
180          List of CTI trigger out signals that will be blocked from becoming
181          active, unless filtering is disabled on the driver.
182
183      arm,trig-conn-name:
184        $ref: /schemas/types.yaml#/definitions/string
185        description:
186          Defines a connection name that will be displayed, if the cpu or
187          arm,cs-dev-assoc properties are not being used in this connection.
188          Principle use for CTI that are connected to non-CoreSight devices, or
189          external IO.
190
191    anyOf:
192      - required:
193          - arm,trig-in-sigs
194      - required:
195          - arm,trig-out-sigs
196    oneOf:
197      - required:
198          - arm,trig-conn-name
199      - required:
200          - cpu
201      - required:
202          - arm,cs-dev-assoc
203    required:
204      - reg
205
206required:
207  - compatible
208  - reg
209  - clocks
210  - clock-names
211
212if:
213  properties:
214    compatible:
215      contains:
216        const: arm,coresight-cti-v8-arch
217
218then:
219  required:
220    - cpu
221
222unevaluatedProperties: false
223
224examples:
225  # minimum CTI definition. DEVID register used to set number of triggers.
226  - |
227    cti@20020000 {
228      compatible = "arm,coresight-cti", "arm,primecell";
229      reg = <0x20020000 0x1000>;
230
231      clocks = <&soc_smc50mhz>;
232      clock-names = "apb_pclk";
233    };
234  #  v8 architecturally defined CTI - CPU + ETM connections generated by the
235  #  driver according to the v8 architecture specification.
236  - |
237    cti@859000 {
238      compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
239                   "arm,primecell";
240      reg = <0x859000 0x1000>;
241
242      clocks = <&soc_smc50mhz>;
243      clock-names = "apb_pclk";
244
245      cpu = <&CPU1>;
246      arm,cs-dev-assoc = <&etm1>;
247    };
248  # Implementation defined CTI - CPU + ETM connections explicitly defined..
249  # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
250  # #size-cells and #address-cells are required if trig-conns@ nodes present.
251  - |
252    #include <dt-bindings/arm/coresight-cti-dt.h>
253
254    cti@858000 {
255      compatible = "arm,coresight-cti", "arm,primecell";
256      reg = <0x858000 0x1000>;
257
258      clocks = <&soc_smc50mhz>;
259      clock-names = "apb_pclk";
260
261      arm,cti-ctm-id = <1>;
262
263      #address-cells = <1>;
264      #size-cells = <0>;
265
266      trig-conns@0 {
267            reg = <0>;
268            arm,trig-in-sigs = <4 5 6 7>;
269            arm,trig-in-types = <ETM_EXTOUT
270                                 ETM_EXTOUT
271                                 ETM_EXTOUT
272                                 ETM_EXTOUT>;
273            arm,trig-out-sigs = <4 5 6 7>;
274            arm,trig-out-types = <ETM_EXTIN
275                                  ETM_EXTIN
276                                  ETM_EXTIN
277                                  ETM_EXTIN>;
278            arm,cs-dev-assoc = <&etm0>;
279      };
280
281      trig-conns@1 {
282            reg = <1>;
283            cpu = <&CPU0>;
284            arm,trig-in-sigs = <0 1>;
285            arm,trig-in-types = <PE_DBGTRIGGER
286                                 PE_PMUIRQ>;
287            arm,trig-out-sigs=<0 1 2 >;
288            arm,trig-out-types = <PE_EDBGREQ
289                                  PE_DBGRESTART
290                                  PE_CTIIRQ>;
291
292            arm,trig-filters = <0>;
293      };
294    };
295  # Implementation defined CTI - non CoreSight component connections.
296  - |
297    cti@20110000 {
298      compatible = "arm,coresight-cti", "arm,primecell";
299      reg = <0x20110000 0x1000>;
300
301      clocks = <&soc_smc50mhz>;
302      clock-names = "apb_pclk";
303
304      #address-cells = <1>;
305      #size-cells = <0>;
306
307      trig-conns@0 {
308        reg = <0>;
309        arm,trig-in-sigs=<0>;
310        arm,trig-in-types=<GEN_INTREQ>;
311        arm,trig-out-sigs=<0>;
312        arm,trig-out-types=<GEN_HALTREQ>;
313        arm,trig-conn-name = "sys_profiler";
314      };
315
316      trig-conns@1 {
317        reg = <1>;
318        arm,trig-out-sigs=<2 3>;
319        arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
320        arm,trig-conn-name = "watchdog";
321      };
322
323      trig-conns@2 {
324        reg = <2>;
325        arm,trig-in-sigs=<1 6>;
326        arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
327        arm,trig-conn-name = "g_counter";
328      };
329    };
330
331...
332