1*92c2b1c1SRob Herring# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2*92c2b1c1SRob Herring# Copyright 2021, Arm Ltd 3*92c2b1c1SRob Herring%YAML 1.2 4*92c2b1c1SRob Herring--- 5*92c2b1c1SRob Herring$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" 6*92c2b1c1SRob Herring$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*92c2b1c1SRob Herring 8*92c2b1c1SRob Herringtitle: ARM Trace Buffer Extensions 9*92c2b1c1SRob Herring 10*92c2b1c1SRob Herringmaintainers: 11*92c2b1c1SRob Herring - Anshuman Khandual <anshuman.khandual@arm.com> 12*92c2b1c1SRob Herring 13*92c2b1c1SRob Herringdescription: | 14*92c2b1c1SRob Herring Arm Trace Buffer Extension (TRBE) is a per CPU component 15*92c2b1c1SRob Herring for storing trace generated on the CPU to memory. It is 16*92c2b1c1SRob Herring accessed via CPU system registers. The software can verify 17*92c2b1c1SRob Herring if it is permitted to use the component by checking the 18*92c2b1c1SRob Herring TRBIDR register. 19*92c2b1c1SRob Herring 20*92c2b1c1SRob Herringproperties: 21*92c2b1c1SRob Herring $nodename: 22*92c2b1c1SRob Herring const: "trbe" 23*92c2b1c1SRob Herring compatible: 24*92c2b1c1SRob Herring items: 25*92c2b1c1SRob Herring - const: arm,trace-buffer-extension 26*92c2b1c1SRob Herring 27*92c2b1c1SRob Herring interrupts: 28*92c2b1c1SRob Herring description: | 29*92c2b1c1SRob Herring Exactly 1 PPI must be listed. For heterogeneous systems where 30*92c2b1c1SRob Herring TRBE is only supported on a subset of the CPUs, please consult 31*92c2b1c1SRob Herring the arm,gic-v3 binding for details on describing a PPI partition. 32*92c2b1c1SRob Herring maxItems: 1 33*92c2b1c1SRob Herring 34*92c2b1c1SRob Herringrequired: 35*92c2b1c1SRob Herring - compatible 36*92c2b1c1SRob Herring - interrupts 37*92c2b1c1SRob Herring 38*92c2b1c1SRob HerringadditionalProperties: false 39*92c2b1c1SRob Herring 40*92c2b1c1SRob Herringexamples: 41*92c2b1c1SRob Herring 42*92c2b1c1SRob Herring - | 43*92c2b1c1SRob Herring #include <dt-bindings/interrupt-controller/arm-gic.h> 44*92c2b1c1SRob Herring 45*92c2b1c1SRob Herring trbe { 46*92c2b1c1SRob Herring compatible = "arm,trace-buffer-extension"; 47*92c2b1c1SRob Herring interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 48*92c2b1c1SRob Herring }; 49*92c2b1c1SRob Herring... 50