1*41e39584SRui Miguel Silva# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*41e39584SRui Miguel Silva%YAML 1.2 3*41e39584SRui Miguel Silva--- 4*41e39584SRui Miguel Silva$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# 5*41e39584SRui Miguel Silva$schema: http://devicetree.org/meta-schemas/core.yaml# 6*41e39584SRui Miguel Silva 7*41e39584SRui Miguel Silvatitle: ARM Corstone1000 Device Tree Bindings 8*41e39584SRui Miguel Silva 9*41e39584SRui Miguel Silvamaintainers: 10*41e39584SRui Miguel Silva - Vishnu Banavath <vishnu.banavath@arm.com> 11*41e39584SRui Miguel Silva - Rui Miguel Silva <rui.silva@linaro.org> 12*41e39584SRui Miguel Silva 13*41e39584SRui Miguel Silvadescription: |+ 14*41e39584SRui Miguel Silva ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that 15*41e39584SRui Miguel Silva provides a flexible compute architecture that combines Cortex‑A and Cortex‑M 16*41e39584SRui Miguel Silva processors. 17*41e39584SRui Miguel Silva 18*41e39584SRui Miguel Silva Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion 19*41e39584SRui Miguel Silva systems for M-Class (or other) processors for adding sensors, connectivity, 20*41e39584SRui Miguel Silva video, audio and machine learning at the edge System and security IPs to build 21*41e39584SRui Miguel Silva a secure SoC for a range of rich IoT applications, for example gateways, smart 22*41e39584SRui Miguel Silva cameras and embedded systems. 23*41e39584SRui Miguel Silva 24*41e39584SRui Miguel Silva Integrated Secure Enclave providing hardware Root of Trust and supporting 25*41e39584SRui Miguel Silva seamless integration of the optional CryptoCell™-312 cryptographic 26*41e39584SRui Miguel Silva accelerator. 27*41e39584SRui Miguel Silva 28*41e39584SRui Miguel Silvaproperties: 29*41e39584SRui Miguel Silva $nodename: 30*41e39584SRui Miguel Silva const: '/' 31*41e39584SRui Miguel Silva compatible: 32*41e39584SRui Miguel Silva oneOf: 33*41e39584SRui Miguel Silva - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA 34*41e39584SRui Miguel Silva implementation of the Corstone1000 in the MPS3 prototyping board. See 35*41e39584SRui Miguel Silva ARM document DAI0550. 36*41e39584SRui Miguel Silva items: 37*41e39584SRui Miguel Silva - const: arm,corstone1000-mps3 38*41e39584SRui Miguel Silva - description: Corstone1000 FVP is the Fixed Virtual Platform 39*41e39584SRui Miguel Silva implementation of this system. See ARM ecosystems FVP's. 40*41e39584SRui Miguel Silva items: 41*41e39584SRui Miguel Silva - const: arm,corstone1000-fvp 42*41e39584SRui Miguel Silva 43*41e39584SRui Miguel SilvaadditionalProperties: true 44*41e39584SRui Miguel Silva 45*41e39584SRui Miguel Silva... 46